DSP例程DA转换程序为什么不用指定GPIO输出?

2019-07-18 15:51发布

看了一个DA的例程,例程里并没有指定DA的输出端口,但是给定了地址。板子上连接到DA芯片输出引脚的插针有DA输出。这是什么原理。是因为数据总线直接访问这个地址,把数据发送到DA芯片的吗?求解.
  1. #include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
  2. #include "DSP2833x_Examples.h"   // DSP2833x Examples Include File
  3. #include <math.h>

  4. void InitXintf(void);
  5. #define DA_CHA                *(Uint16 *)0x4100
  6. #define DA_CHB                *(Uint16 *)0x4102
  7. #define DA_CHC                *(Uint16 *)0x4104
  8. #define DA_CHD                *(Uint16 *)0x4106
  9. #define DA_TRANS        *(Uint16 *)0x47ff

  10. void main(void)
  11. {
  12.    Uint16 CHA_DATA = 0;
  13.    Uint16 CHB_DATA = 0;
  14.    Uint16 CHC_DATA = 0;
  15.    Uint16 CHD_DATA = 0;
  16.    Uint16 flagA = 0;

  17.    InitSysCtrl();

  18.    DINT;


  19.    InitPieCtrl();


  20.    IER = 0x0000;
  21.    IFR = 0x0000;


  22.    InitPieVectTable();
  23.    
  24.    InitXintf();

  25.    while(1)
  26.    {        DA_TRANS = 1;
  27.         if(flagA)
  28.         {
  29.                 CHA_DATA -= 100;
  30.                 if(CHA_DATA == 0)
  31.         {
  32.                         flagA = 0;
  33.                 }
  34.         }
  35.         else
  36.         {
  37.                 CHA_DATA += 100;
  38.                 if(CHA_DATA == 4000)
  39.                 {
  40.                         flagA = 1;
  41.                 }
  42.         }

  43.         if(flagA)
  44.                 CHB_DATA = 0;
  45.         else
  46.                 CHB_DATA = 4000;

  47.         if(CHC_DATA == 4000)
  48.                 CHC_DATA = 0;
  49.         else
  50.                 CHC_DATA += 100;

  51.         CHD_DATA = 2047 * sin((float)(2 * 3.14 * (float)CHC_DATA / 4000.0)) + 2048;

  52.         DA_CHA = CHA_DATA;//三角波
  53.         DA_CHB = CHB_DATA;//方波
  54.         DA_CHC = CHC_DATA;//锯齿波
  55.         DA_CHD = CHD_DATA;//正弦波
  56.         DA_TRANS = 0;
  57.         DELAY_US(10);

  58.    }
  59. }
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7条回答
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2019-07-19 17:33
eefas 发表于 2017-2-21 22:32
设置在InitXintf这个函数里面。

EALLOW;
    XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
    // No write buffering
    XintfRegs.XINTCNF2.bit.WRBUFF = 0;
    // XCLKOUT is enabled
    XintfRegs.XINTCNF2.bit.CLKOFF = 0;
    // XCLKOUT = XTIMCLK/2
    XintfRegs.XINTCNF2.bit.CLKMODE = 1;


    // Zone 0------------------------------------
    // When using ready, ACTIVE must be 1 or greater
    // Lead must always be 1 or greater
    // Zone write timing
    XintfRegs.XTIMING0.bit.XWRLEAD = 3;
    XintfRegs.XTIMING0.bit.XWRACTIVE = 7;
    XintfRegs.XTIMING0.bit.XWRTRAIL = 3;
    // Zone read timing
    XintfRegs.XTIMING0.bit.XRDLEAD = 3;
    XintfRegs.XTIMING0.bit.XRDACTIVE = 7;
    XintfRegs.XTIMING0.bit.XRDTRAIL = 3;

    // double all Zone read/write lead/active/trail timing
    XintfRegs.XTIMING0.bit.X2TIMING = 1;

    // Zone will sample XREADY signal
    XintfRegs.XTIMING0.bit.USEREADY = 1;
    XintfRegs.XTIMING0.bit.READYMODE = 1;  // sample asynchronous

    // Size must be either:
    // 0,1 = x32 or
    // 1,1 = x16 other values are reserved
    XintfRegs.XTIMING0.bit.XSIZE = 3;

    // Zone 6------------------------------------
    // When using ready, ACTIVE must be 1 or greater
    // Lead must always be 1 or greater
    // Zone write timing
    XintfRegs.XTIMING6.bit.XWRLEAD = 3;
    XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
    XintfRegs.XTIMING6.bit.XWRTRAIL = 3;
    // Zone read timing
    XintfRegs.XTIMING6.bit.XRDLEAD = 3;
    XintfRegs.XTIMING6.bit.XRDACTIVE = 7;
    XintfRegs.XTIMING6.bit.XRDTRAIL = 3;

    // double all Zone read/write lead/active/trail timing
    XintfRegs.XTIMING6.bit.X2TIMING = 1;

    // Zone will sample XREADY signal
    XintfRegs.XTIMING6.bit.USEREADY = 1;
    XintfRegs.XTIMING6.bit.READYMODE = 1;  // sample asynchronous

    // Size must be either:
    // 0,1 = x32 or
    // 1,1 = x16 other values are reserved
    XintfRegs.XTIMING6.bit.XSIZE = 3;


    // Zone 7------------------------------------
    // When using ready, ACTIVE must be 1 or greater
    // Lead must always be 1 or greater
    // Zone write timing
    XintfRegs.XTIMING7.bit.XWRLEAD = 3;
    XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
    XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
    // Zone read timing
    XintfRegs.XTIMING7.bit.XRDLEAD = 3;
    XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
    XintfRegs.XTIMING7.bit.XRDTRAIL = 3;

    // double all Zone read/write lead/active/trail timing
    XintfRegs.XTIMING7.bit.X2TIMING = 1;

    // Zone will sample XREADY signal
    XintfRegs.XTIMING7.bit.USEREADY = 1;
    XintfRegs.XTIMING7.bit.READYMODE = 1;  // sample asynchronous

    // Size must be either:
    // 0,1 = x32 or
    // 1,1 = x16 other values are reserved
    XintfRegs.XTIMING7.bit.XSIZE = 3;

    // Bank switching
    // Assume Zone 7 is slow, so add additional BCYC cycles
    // when ever switching from Zone 7 to another Zone.
    // This will help avoid bus contention.
    XintfRegs.XBANK.bit.BANK = 7;
    XintfRegs.XBANK.bit.BCYC = 7;
    EDIS;
   //Force a pipeline flush to ensure that the write to
   //the last register configured occurs before returning.

   InitXintf16Gpio();
// InitXintf32Gpio();

   asm(" RPT #7 || NOP");

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