刚刚找到了. 原来datasheet里就有.

All devices feature:
 512 Kbytes of AXI-SRAM mapped onto AXI bus on D1 domain.
 SRAM1 mapped on D2 domain: 128 Kbytes
 SRAM2 mapped on D2 domain: 128 Kbytes
 SRAM3 mapped on D2 domain: 32 Kbytes
 SRAM4 mapped on D3 domain: 64 Kbytes
 4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses,
and is retained in Standby or VBAT mode.
 RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories. either They can be accessed
either from the CPU or the MDMA (even in Sleep mode) through a specific AHB slave
of the CPU(AHBP):
– 64 Kbytes of ITCM-RAM (instruction RAM)
This RAM is connected to ITCM 64-bit interface designed for execution of critical
real-times routines by the CPU.
– 128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
The DTCM-RAM could be used for critical real-time data, such as interrupt service
routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for
load/store operations) thanks to the Cortex®-M7 dual issue capability.
The MDMA can be used to load code or data in ITCM or DTCM RAMs.

datasheet里还有图有真相..


但这一章..

Memory mapping

Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.