本帖最后由 Eternal单人行 于 2017-6-8 16:20 编辑
根据原子哥的模板进行了修改，但没任何反馈数据，求大神们指点怎么使用SPI1与DMA的数据传递
[mw_shl_code=c,true]DMAPtoM_Config(DMA2_Stream3,DMA_Channel_3,(u32)&SPI1->DR,(u32)&DMA_Buffer,12);
DMAPtoM_Config(DMA2_Stream7,DMA_Channel_4,(u32)&USART1->DR,(u32)&DMA_Buffer,12);
W25QXX_CS=0;
SPI1_ReadWriteByte_flash(W25X_ReadData);
while(1)
{
if(DMA_GetFlagStatus(DMA2_Stream3,DMA_FLAG_TCIF3)!=RESET)
{
DMA_ClearFlag(DMA2_Stream3,DMA_FLAG_TCIF3);
break;
}
W25QXX_CS=1;
}
USART_DMACmd(USART1,USART_DMAReq_Tx,ENABLE);
MYDMA_Enable(DMA2_Stream7,12);
while(1)
{
if(DMA_GetFlagStatus(DMA2_Stream7,DMA_FLAG_TCIF7)!=RESET)
{
DMA_ClearFlag(DMA2_Stream7,DMA_FLAG_TCIF7);
break;
}
}[/mw_shl_code]
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[mw_shl_code=c,true]void SPI1_DMA_Config(u32 mar,u16 ndtr)
{
DMA_InitTypeDef DMA_InitStructure;
/**DMA2_Stream2 ,DMA2_Channel3 SPI RX**/
DMA_DeInit(DMA2_Stream2);
DMA_InitStructure.DMA_Channel=DMA_Channel_3;
DMA_InitStructure.DMA_PeripheralBaseAddr =(u32)&SPI1->DR;//DMAíaéèμØÖ·
DMA_InitStructure.DMA_Memory0BaseAddr = mar;//DMA ′æ′￠Æ÷0μØÖ·
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;//íaéèμ½′æ′￠Æ÷
DMA_InitStructure.DMA_BufferSize = ndtr;//êy¾Y′«êäá¿
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;//íaéè·ÇÔöá¿Ä￡ê½
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;//′æ′￠Æ÷Ôöá¿Ä￡ê½
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;//íaéèêy¾Y3¤¶è:8λ
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;//′æ′￠Æ÷êy¾Y3¤¶è:8λ
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;// ê1óÃÆÕí¨Ä￡ê½
DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;//¸ßμèóÅÏ輶
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;//′æ′￠Æ÷í»·￠μ￥′Î′«êä
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;//íaéèí»·￠μ￥′Î′«êä
DMA_Init(DMA2_Stream2, &DMA_InitStructure);//3õê¼»ˉDMA Stream
DMA_ITConfig(DMA2_Stream2, DMA_IT_TC, ENABLE);
/* Enable SPI1 DMA RX request */
SPI1->CR2 |= 1<<0; //½óêÕ»o3åÇøDMAê1Äü
DMA_Cmd(DMA2_Stream2, ENABLE);
/**DMA2_Stream3 ,DMA2_Channel3 SPI TX**/
DMA_DeInit(DMA2_Stream3);
DMA_InitStructure.DMA_Channel=DMA_Channel_3;
DMA_InitStructure.DMA_PeripheralBaseAddr =(u32)&SPI1->DR;//DMAíaéèμØÖ·
DMA_InitStructure.DMA_Memory0BaseAddr = mar;//DMA ′æ′￠Æ÷0μØÖ·
DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;//′æ′￠Æ÷μ½íaéè
DMA_InitStructure.DMA_BufferSize = ndtr;//êy¾Y′«êäá¿
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;//íaéè·ÇÔöá¿Ä￡ê½
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;//′æ′￠Æ÷Ôöá¿Ä￡ê½
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;//íaéèêy¾Y3¤¶è:8λ
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;//′æ′￠Æ÷êy¾Y3¤¶è:8λ
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;// ê1óÃÆÕí¨Ä￡ê½
DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;//¸ßμèóÅÏ輶
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;//′æ′￠Æ÷í»·￠μ￥′Î′«êä
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;//íaéèí»·￠μ￥′Î′«êä
DMA_Init(DMA2_Stream3, &DMA_InitStructure);//3õê¼»ˉDMA Stream
DMA_ITConfig(DMA2_Stream3, DMA_IT_TC, ENABLE); //?? DMA1_Channel3 ??????
DMA_ITConfig(DMA2_Stream3, DMA_IT_TE, ENABLE); //?? DMA1_Channel3 ??????
/* Enable SPI1 DMA TX request */
SPI1->CR2 |= 1<<1; //?????DMA??
DMA_Cmd(DMA2_Stream3, DISABLE); //?? DMA ?? DMA1_Channel3
}
/******************************************
*oˉêyÃû￡oSPI1_Send
*1| Äü￡oSPIμÄDMA·½ê½·￠Ëí
*êä èë￡oÄú′æμØÖ·buff,′«êä×Ö½ú3¤¶èlen
*êä 3ö￡oÎT
*******************************************/
void SPI1_Send( u8 *buff, u32 len )
{
DMA2_Stream3->PAR = SPI1->DR; //íaéèμØÖ·
DMA2_Stream3->M0AR = (u32)buff; //Äú′æμØÖ·
DMA2_Stream3->NDTR = len ; //′«êä3¤¶è
DMA2_Stream3->CR = (0 << 14) | // ·Ç′æ′￠Æ÷μ½′æ′￠Æ÷Ä￡ê½
(2 << 12) | // í¨μàóÅÏ輶¸ß
(0 << 11) | // ′æ′￠Æ÷êy¾Y¿í¶è8bit
(0 << 10) | // ′æ′￠Æ÷êy¾Y¿í¶è8bit
(0 << 9) | // íaéèêy¾Y¿í¶è8bit
(0 << 8) | // íaéèêy¾Y¿í¶è8bit
(1 << 7) | // ′æ′￠Æ÷μØÖ·Ôöá¿Ä￡ê½
(0 << 6) | // íaéèμØÖ·Ôöá¿Ä￡ê½(2»Ôö)
(0 << 5) | // ·ÇÑ-»·Ä￡ê½
(1 << 4) | // ′«êä·½ê½ Äú′æ->íaéè
(1 << 3) | // ÔêDí′«êä′íÎóÖD¶Ï
(0 << 2) | // ÔêDí°ë′«êäÖD¶Ï
(1 << 1) | // ÔêDí′«êäíê3éÖD¶Ï
(1); // í¨μà¿aÆô
}
/******************************************
*oˉêyÃû￡oSPI1_Recive
*1| Äü￡oSPIμÄDMA·½ê½½óêÕ
*êä èë￡oÄú′æμØÖ·buff,′«êä×Ö½ú3¤¶èlen
*êä 3ö￡oÎT
*******************************************/
void SPI1_Recive( u8 *buff, u32 len )
{
DMA2_Stream2->CR &= ~( 1 << 0 ); //1رÕêy¾Yá÷2
DMA2_Stream2->PAR = SPI1->DR; //íaéèμØÖ·
DMA2_Stream2->M0AR = (u32)buff; //Äú′æμØÖ·
DMA2_Stream2->NDTR = len ; //′«êä3¤¶è
DMA2_Stream2->CR = (0 << 14) | // ·Ç′æ′￠Æ÷μ½′æ′￠Æ÷Ä￡ê½
(2 << 12) | // í¨μàóÅÏ輶¸ß
(0 << 11) | // ′æ′￠Æ÷êy¾Y¿í¶è8bit
(0 << 10) | // ′æ′￠Æ÷êy¾Y¿í¶è8bit
(0 << 9) | // íaéèêy¾Y¿í¶è8bit
(0 << 8) | // íaéèêy¾Y¿í¶è8bit
(1 << 7) | // ′æ′￠Æ÷μØÖ·Ôöá¿Ä￡ê½
(0 << 6) | // íaéèμØÖ·Ôöá¿Ä￡ê½(2»Ôö)
(0 << 5) | // ·ÇÑ-»·Ä￡ê½
(0 << 4) | // ′«êä·½ê½ íaéè->Äú′æ
(0 << 3) | // ÔêDí′«êä′íÎóÖD¶Ï
(0 << 2) | // ÔêDí°ë′«êäÖD¶Ï
(1 << 1) | // ÔêDí′«êäíê3éÖD¶Ï
(1); // í¨μà¿aÆô
}[/mw_shl_code]
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