最近在做一个STM32F4驱动K9F8G08U0M,有网上找了一个驱动K9F1G08U0C的例程，想基于那个改，结果只能获取ID，写入非0XFF数据后，返回全是0xff，
已经把芯片的属性更改了一下：
/* for K9F8G08 */
#define NAND_PAGE_SIZE ((uint16_t)0x1000) /* 4 * 1024 bytes per page w/o Spare Area */
#define NAND_BLOCK_SIZE ((uint16_t)0x0040) /* 64 pages per block */
#define NAND_ZONE_SIZE ((uint16_t)0x1000) /* 4096 Block per zone */
#define NAND_SPARE_AREA_SIZE ((uint16_t)0x0080) /* last 128 bytes as spare area */
#define NAND_MAX_ZONE ((uint16_t)0x0001) /* 1 zones of 1024 block */
有没可以指导一下的？在线等啊
把部分程序附上！
/////////////////////////////fsmc_nand.h////////////////////////////////////////////////
/* NAND Area definition for STM3210E-EVAL Board RevD */
#define CMD_AREA (uint32_t)(1<<17) /* A17 = CLE high */
#define ADDR_AREA (uint32_t)(1<<16) /* A18 = ALE high */
#define DATA_AREA ((uint32_t)0x00000000)
/* FSMC NAND memory command */
#define NAND_CMD_AREA_A ((u8)0x00)
#define NAND_CMD_AREA_B ((u8)0x200)
#define NAND_CMD_AREA_C ((u8)0x400)
#define NAND_CMD_AREA_D ((u8)0x600)
#define NAND_CMD_AREA_E ((u8)0x800)
#define NAND_CMD_AREA_F ((u8)0x810)
#define NAND_CMD_AREA_G ((u8)0x820)
#define NAND_CMD_AREA_H ((u8)0x830)
#define NAND_CMD_READ0 ((u8)0x00)
#define NAND_CMD_READ_TRUE1 ((u8)0x30)
#define NAND_CMD_WRITE0 ((u8)0x80)
#define NAND_CMD_WRITE_TRUE1 ((u8)0x10)
#define NAND_CMD_ERASE0 ((u8)0x60)
#define NAND_CMD_ERASE1 ((u8)0xD0)
#define NAND_CMD_READID ((u8)0x90)
#define NAND_CMD_STATUS ((u8)0x70)
#define NAND_CMD_LOCK_STATUS ((u8)0x7A)
#define NAND_CMD_RESET ((u8)0xFF)
/* NAND memory status */
#define NAND_VALID_ADDRESS ((u32)0x00000100)
#define NAND_INVALID_ADDRESS ((u32)0x00000200)
#define NAND_TIMEOUT_ERROR ((u32)0x00000400)
#define NAND_BUSY ((u32)0x00000000)
#define NAND_ERROR ((u32)0x00000001)
#define NAND_READY ((u32)0x00000040)
/* FSMC NAND memory address computation */
#define ADDR_1st_CYCLE(ADDR) 0x00 /* 1st addressing cycle :COLUMN ADDRESS*/
#define ADDR_2nd_CYCLE(ADDR) 0x00 /* 2nd addressing cycle :COLUMN ADDRESS*/
#define ADDR_3rd_CYCLE(ADDR) (u8)((ADDR)& 0xFF) /* 3rd addressing cycle :ROW ADDRESS*/
#define ADDR_4th_CYCLE(ADDR) (u8)(((ADDR)& 0xFF00) >> 8) /* 4th addressing cycle :ROW ADDRESS*/
#define ADDR_5fh_CYCLE(ADDR) (u8)(((ADDR)& 0x10000) >> 16) /* 5th addressing cycle :ROW ADDRESS*/
/* for K9F8G08 */
#define NAND_PAGE_SIZE ((uint16_t)0x1000) /* 4 * 1024 bytes per page w/o Spare Area */
#define NAND_BLOCK_SIZE ((uint16_t)0x0040) /* 64 pages per block */
#define NAND_ZONE_SIZE ((uint16_t)0x1000) /* 4096 Block per zone */
#define NAND_SPARE_AREA_SIZE ((uint16_t)0x0080) /* last 128 bytes as spare area */
#define NAND_MAX_ZONE ((uint16_t)0x0001) /* 1 zones of 1024 block */
////////////////////////////////fsmc_nand.c/////////////////////////////////////////////
/* Includes ------------------------------------------------------------------*/
#include "fsmc_nand.h"
#include "delay.h"
#include "sys.h"
/* Private define ------------------------------------------------------------*/
#define NAND_FLASH_START_ADDR ((uint32_t)0x70000000)
#define FSMC_Bank_NAND FSMC_Bank2_NAND
#define Bank_NAND_ADDR Bank2_NAND_ADDR
#define Bank2_NAND_ADDR ((u32)0x70000000)
#define RB_VALUE() GPIO_ReadInputDataBit(GPIOD,GPIO_Pin_6)
#define ROW_ADDRESS (Address.Page + (Address.Block + (Address.Zone * NAND_ZONE_SIZE)) * NAND_BLOCK_SIZE)
#define SpareArea_ADDRESS (Address.Page + (Address.Block + (Address.Zone * NAND_ZONE_SIZE)) * NAND_BLOCK_SIZE + NAND_CMD_AREA_E)
/* Private variables ---------------------------------------------------------*/
static uint8_t TxBuffer [NAND_PAGE_SIZE];
static uint8_t RxBuffer [NAND_PAGE_SIZE];
/*******************************************************************************
* Function Name : FSMC_NAND_Init
* Description : Configures the FSMC and GPIOs to interface with the NAND memory.
* This function must be called before any write/read operation
* on the NAND.
* Input : None
* Output : None
* Return : None
* Attention : None
*******************************************************************************/
void FSMC_NAND_Init(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
FSMC_NAND_PCCARDTimingInitTypeDef p;
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOE , ENABLE);
/*-- GPIO Configuration ------------------------------------------------------*/
/* CLE, ALE, D0->D3, NOE, NWE and NCE2 NAND pin configuration */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC,ENABLE);
/* D0->D3,*/
GPIO_PinAFConfig(GPIOD, GPIO_PinSource14 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource15 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource0 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource1 , GPIO_AF_FSMC);
/* D4->D7 NAND pin configuration */
GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FSMC);
/*-- GPIO Configuration ------------------------------------------------------*/
/* CLE, ALE, D0->D7, NOE, NWE and NCE2 NAND pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 |GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/* D4->D7 NAND pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
GPIO_Init(GPIOE, &GPIO_InitStructure);
/*CLE, ALE */
GPIO_PinAFConfig(GPIOD, GPIO_PinSource11 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource12 , GPIO_AF_FSMC);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 ;
GPIO_Init(GPIOD, &GPIO_InitStructure);
// /*enable PD13*/
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource13 , GPIO_AF_FSMC);
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13;
// GPIO_Init(GPIOD, &GPIO_InitStructure);
/*NOE, NWE*/
GPIO_PinAFConfig(GPIOD, GPIO_PinSource4 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource5 , GPIO_AF_FSMC);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/*PD7 -> NCE2 PG9 -> NCE3*/
GPIO_PinAFConfig(GPIOD, GPIO_PinSource7 , GPIO_AF_FSMC);
//GPIO_PinAFConfig(GPIOG, GPIO_PinSource9 , GPIO_AF_FSMC);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
//GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
GPIO_Init(GPIOD, &GPIO_InitStructure);
//GPIO_Init(GPIOG, &GPIO_InitStructure);
/*NWAIT*/
GPIO_PinAFConfig(GPIOD, GPIO_PinSource6 , GPIO_AF_FSMC);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN ;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/*-- FSMC Configuration ------------------------------------------------------*/
p.FSMC_SetupTime = 0xf5;
p.FSMC_WaitSetupTime = 0xf3;
p.FSMC_HoldSetupTime = 0xf2;
p.FSMC_HiZSetupTime = 0xf5;
FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND;
FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Disable;
FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable;
FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_2048Bytes;
FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0xa1;
FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x15;
FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
FSMC_NANDInit(&FSMC_NANDInitStructure);
/* FSMC NAND Bank Cmd Test */
FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
}
/******************************************************************************
* Function Name : FSMC_NAND_ReadID
* Description : Reads NAND memory's ID.
* Input : - NAND_ID: pointer to a NAND_IDTypeDef structure which will hold
* the Manufacturer and Device ID.
* Output : None
* Return : None
* Attention : None
*******************************************************************************/
void FSMC_NAND_ReadID(NAND_IDTypeDef* NAND_ID)
{
uint32_t data = 0;
/* Send Command to the command area */
*(vu8 *)(NAND_FLASH_START_ADDR | CMD_AREA) = 0x90;
*(vu8 *)(NAND_FLASH_START_ADDR | ADDR_AREA) = 0x00;
/* Sequence to read ID from NAND flash */
// data = *(vu32 *)(NAND_FLASH_START_ADDR | DATA_AREA);
// NAND_ID->Maker_ID = ADDR_1st_CYCLE (data);
// NAND_ID->Device_ID = ADDR_2nd_CYCLE (data);
// NAND_ID->Third_ID = ADDR_3rd_CYCLE (data);
// NAND_ID->Fourth_ID = ADDR_4th_CYCLE (data);
NAND_ID->Maker_ID = *(vu8 *)(NAND_FLASH_START_ADDR | DATA_AREA);
NAND_ID->Device_ID = *(vu8 *)(NAND_FLASH_START_ADDR | DATA_AREA);
NAND_ID->Third_ID = *(vu8 *)(NAND_FLASH_START_ADDR | DATA_AREA);
NAND_ID->Fourth_ID = *(vu8 *)(NAND_FLASH_START_ADDR | DATA_AREA);
NAND_ID->Fifth_ID = *(vu8 *)(NAND_FLASH_START_ADDR | DATA_AREA);
}
/******************************************************************************
* Function Name : FSMC_NAND_WriteSmallPage
* Description : This routine is for writing one or several 512 Bytes Page size.
* Input : - pBuffer: pointer on the Buffer containing data to be written
* - Address: First page address
* - NumPageToWrite: Number of page to write
* Output : None
* Return : New status of the NAND operation. This parameter can be:
* - NAND_TIMEOUT_ERROR: when the previous operation generate
* a Timeout error
* - NAND_READY: when memory is ready for the next operation
* And the new status of the increment address operation. It can be:
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
* Attention : None
*******************************************************************************/
uint32_t FSMC_NAND_WriteSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite)
{
u32 index = 0x00, numpagewritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
u32 status = NAND_READY, size = 2048;
while((NumPageToWrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
{
/* Page write command and address */
*(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(ROW_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_5fh_CYCLE(ROW_ADDRESS);
/* Calculate the size */
size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpagewritten);
/* Write data */
for(; index < size; index++)
{
*(vu8 *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
}
*(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
/* Check status for successful operation */
status = FSMC_NAND_GetStatus();
if(status == NAND_READY)
{
numpagewritten++;
NumPageToWrite--;
/* Calculate Next small page Address */
addressstatus = FSMC_NAND_AddressIncrement(&Address);
}
}
return (status | addressstatus);
}
/******************************************************************************
* Function Name : FSMC_NAND_ReadSmallPage
* Description : This routine is for sequential read from one or several
* 512 Bytes Page size.
* Input : - pBuffer: pointer on the Buffer to fill
* - Address: First page address
* - NumPageToRead: Number of page to read
* Output : None
* Return : New status of the NAND operation. This parameter can be:
* - NAND_TIMEOUT_ERROR: when the previous operation generate
* a Timeout error
* - NAND_READY: when memory is ready for the next operation
* And the new status of the increment address operation. It can be:
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
* Attention : None
*******************************************************************************/
uint32_t FSMC_NAND_ReadSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead)
{
u32 index = 0x00, numpageread = 0x00, addressstatus = NAND_VALID_ADDRESS;
u32 status = NAND_READY, size = 2048;
while((NumPageToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
{
/* Page Read command and page address */
*(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_READ0;
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(ROW_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_5fh_CYCLE(ROW_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_READ_TRUE1;
delay_us(50);
//status = FSMC_NAND_GetStatus();
/* Calculate the size */
size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpageread);
/* Get Data into Buffer */
for(; index < size; index++)
{
pBuffer[index]= *(vu8 *)(Bank_NAND_ADDR | DATA_AREA);
}
numpageread++;
NumPageToRead--;
/* Calculate page address */
addressstatus = FSMC_NAND_AddressIncrement(&Address);
status = FSMC_NAND_GetStatus();
}
// status = FSMC_NAND_GetStatus();
return (status | addressstatus);
}
/******************************************************************************
* Function Name : FSMC_NAND_WriteSpareArea
* Description : This routine write the spare area information for the specified
* pages addresses.
* Input : - pBuffer: pointer on the Buffer containing data to be written
* - Address: First page address
* - NumSpareAreaTowrite: Number of Spare Area to write
* Output : None
* Return : New status of the NAND operation. This parameter can be:
* - NAND_TIMEOUT_ERROR: when the previous operation generate
* a Timeout error
* - NAND_READY: when memory is ready for the next operation
* And the new status of the increment address operation. It can be:
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
* Attention : None
*******************************************************************************/
uint32_t FSMC_NAND_WriteSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite)
{
u32 index = 0x00, numsparesreawritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
u32 status = NAND_READY, size = 0x00;
while((NumSpareAreaTowrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
{
/* Page write Spare area command and address */
*(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(SpareArea_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(SpareArea_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(SpareArea_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(SpareArea_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_5fh_CYCLE(SpareArea_ADDRESS);
/* Calculate the size */
size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparesreawritten);
/* Write the data */
for(; index < size; index++)
{
*(vu8 *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
}
*(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
/* Check status for successful operation */
status = FSMC_NAND_GetStatus();
if(status == NAND_READY)
{
numsparesreawritten++;
NumSpareAreaTowrite--;
/* Calculate Next page Address */
addressstatus = FSMC_NAND_AddressIncrement(&Address);
}
}
return (status | addressstatus);
}
/******************************************************************************
* Function Name : FSMC_NAND_ReadSpareArea
* Description : This routine read the spare area information from the specified
* pages addresses.
* Input : - pBuffer: pointer on the Buffer to fill
* - Address: First page address
* - NumSpareAreaToRead: Number of Spare Area to read
* Output : None
* Return : New status of the NAND operation. This parameter can be:
* - NAND_TIMEOUT_ERROR: when the previous operation generate
* a Timeout error
* - NAND_READY: when memory is ready for the next operation
* And the new status of the increment address operation. It can be:
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
* Attention : None
*******************************************************************************/
uint32_t FSMC_NAND_ReadSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead)
{
u32 numsparearearead = 0x00, index = 0x00, addressstatus = NAND_VALID_ADDRESS;
u32 status = NAND_READY, size = 0x00;
while((NumSpareAreaToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
{
/* Page Read command and page address */
*(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_READ0;
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(SpareArea_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(SpareArea_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(SpareArea_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(SpareArea_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_5fh_CYCLE(SpareArea_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_READ_TRUE1;
delay_us(50);
//status = FSMC_NAND_GetStatus();
/* Data Read */
size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparearearead);
/* Get Data into Buffer */
for ( ;index < size; index++)
{
pBuffer[index] = *(vu8 *)(Bank_NAND_ADDR | DATA_AREA);
}
numsparearearead++;
NumSpareAreaToRead--;
/* Calculate page address */
addressstatus = FSMC_NAND_AddressIncrement(&Address);
status = FSMC_NAND_GetStatus();
}
return (status | addressstatus);
}
/******************************************************************************
* Function Name : FSMC_NAND_EraseBlock
* Description : This routine erase complete block from NAND FLASH
* Input : - Address: Any address into block to be erased
* Output : None
* Return : New status of the NAND operation. This parameter can be:
* - NAND_TIMEOUT_ERROR: when the previous operation generate
* a Timeout error
* - NAND_READY: when memory is ready for the next operation
* Attention : None
*******************************************************************************/
uint32_t FSMC_NAND_EraseBlock(NAND_ADDRESS Address)
{
*(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE0;
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(ROW_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_5fh_CYCLE(ROW_ADDRESS);
*(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE1;
delay_ms(2);
return (FSMC_NAND_GetStatus());
}
/******************************************************************************
* Function Name : FSMC_NAND_Reset
* Description : This routine reset the NAND FLASH
* Input : None
* Output : None
* Return : NAND_READY
* Attention : None
*******************************************************************************/
uint32_t FSMC_NAND_Reset(void)
{
*(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_RESET;
return (NAND_READY);
}
/******************************************************************************
* Function Name : FSMC_NAND_GetStatus
* Description : Get the NAND operation status
* Input : None
* Output : None
* Return : New status of the NAND operation. This parameter can be:
* - NAND_TIMEOUT_ERROR: when the previous operation generate
* a Timeout error
* - NAND_READY: when memory is ready for the next operation
* Attention : None
*******************************************************************************/
uint32_t FSMC_NAND_GetStatus(void)
{
u32 timeout = 0x1000000, status = NAND_READY;
status = FSMC_NAND_ReadStatus();
/* Wait for a NAND operation to complete or a TIMEOUT to occur */
while ((status != NAND_READY) &&( timeout != 0x00))
{
status = FSMC_NAND_ReadStatus();
timeout --;
}
if(timeout == 0x00)
{
status = NAND_TIMEOUT_ERROR;
}
/* Return the operation status */
return (status);
}
/******************************************************************************
* Function Name : FSMC_NAND_ReadStatus
* Description : Reads the NAND memory status using the Read status command
* Input : None
* Output : None
* Return : The status of the NAND memory. This parameter can be:
* - NAND_BUSY: when memory is busy
* - NAND_READY: when memory is ready for the next operation
* - NAND_ERROR: when the previous operation gererates error
* Attention : None
*******************************************************************************/
uint32_t FSMC_NAND_ReadStatus(void)
{
u32 data = 0x00, status = NAND_BUSY;
if(!RB_VALUE()) return (status);
/* Read status operation ------------------------------------ */
*(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_STATUS;
data = *(vu8 *)(Bank_NAND_ADDR);
if((data & NAND_ERROR) == NAND_ERROR)
{
status = NAND_ERROR;
}
else if((data & NAND_READY) == NAND_READY)
{
status = NAND_READY;
}
else
{
status = NAND_BUSY;
}
return (status);
}
/******************************************************************************
* Function Name : NAND_AddressIncrement
* Description : Increment the NAND memory address
* Input : - Address: address to be incremented.
* Output : None
* Return : The new status of the increment address operation. It can be:
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
* Attention : None
*******************************************************************************/
uint32_t FSMC_NAND_AddressIncrement(NAND_ADDRESS* Address)
{
u32 status = NAND_VALID_ADDRESS;
Address->Page++;
if(Address->Page == NAND_BLOCK_SIZE)
{
Address->Page = 0;
Address->Block++;
if(Address->Block == NAND_ZONE_SIZE)
{
Address->Block = 0;
Address->Zone++;
if(Address->Zone == NAND_MAX_ZONE)
{
status = NAND_INVALID_ADDRESS;
}
}
}
return (status);
}
static void FSMC_NAND_GET_DEVICEID()
{
NAND_IDTypeDef NAND_ID;
/* ¼ì2aNAND Flash */
// while(1)
{
FSMC_NAND_ReadID(&NAND_ID);
printf("Nand Flash ID = %02X,%02X,%02X,%02X,%02x
",NAND_ID.Maker_ID, NAND_ID.Device_ID,
NAND_ID.Third_ID, NAND_ID.Fourth_ID,NAND_ID.Fifth_ID );
delay_ms(500);
if ((NAND_ID.Maker_ID == 0xEC) && (NAND_ID.Device_ID == 0xD3)
&& (NAND_ID.Third_ID == 0x10) && (NAND_ID.Fourth_ID == 0xA6))
{
printf("Type = K9F8G08u0m
");
}
else if ((NAND_ID.Maker_ID == 0xEC) && (NAND_ID.Device_ID == 0xF1)
&& (NAND_ID.Third_ID == 0x80) && (NAND_ID.Fourth_ID == 0x15))
{
printf("Type = K9F1G08U0A
");
}
else if ((NAND_ID.Maker_ID == 0xEC) && (NAND_ID.Device_ID == 0xF1)
&& (NAND_ID.Third_ID == 0x00) && (NAND_ID.Fourth_ID == 0x95))
{
printf("Type = K9F1G08U0B
");
}
else if ((NAND_ID.Maker_ID == 0xAD) && (NAND_ID.Device_ID == 0xF1)
&& (NAND_ID.Third_ID == 0x80) && (NAND_ID.Fourth_ID == 0x1D))
{
printf("Type = HY27UF081G2A
");
}
else
{
printf("Type = Unknow
");
}
}
}
/******************************************************************************
* Function Name : FSMC_NAND_Test
* Description : NAND test
* Input : None
* Output : None
* Return : None
* Attention : None
*******************************************************************************/
void FSMC_NAND_Test(void)
{
uint16_t index;
uint16_t j;
uint32_t flag;
NAND_IDTypeDef NAND_ID;
NAND_ADDRESS WriteReadAddr;
FSMC_NANDDeInit(FSMC_Bank2_NAND);
FSMC_NAND_Init();
delay_ms(100);
FSMC_NAND_GET_DEVICEID();
delay_ms(100);
/* NAND memory address to write to */
WriteReadAddr.Zone = 0x00;
WriteReadAddr.Block = 0x00;
WriteReadAddr.Page = 0x00;
/* Erase the NAND first Block */
if(FSMC_NAND_EraseBlock(WriteReadAddr)== NAND_READY)
{
printf("erase block success!
");
}
else
{
printf("erase block fail!
");
}
delay_ms(100);
/* Write data to FSMC NOR memory */
/* Fill the buffer to send */
for (index = 0; index < NAND_PAGE_SIZE; index++ )
{
TxBuffer[index] = index;
}
// while(1)
{
flag = FSMC_NAND_WriteSmallPage(TxBuffer, WriteReadAddr, 1);
printf("write data
");
delay_ms(1000);
}
if(flag==0x140)
{
printf("write date success!
");
}
else
{
printf("write date fail! state:%x
",flag);
}
/* Read back the written data */
flag = FSMC_NAND_ReadSmallPage (RxBuffer, WriteReadAddr, 1);
if(flag == 0x140)
{
printf("read date success!
");
}
else
{
printf("read date fail! state:%x
",flag);
}
printf("
Written to the number of￡o
");
for(j = 0; j < 128; j++)
printf("%x
",TxBuffer[j]);
printf("
Read several￡o
");
for(j = 0; j < 128; j++)
printf("%x
",RxBuffer[j]);
}
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