STM32 红外发射Timer1 ch1 PWM输出

2019-07-21 07:55发布

之前做红外发射,在网上都找不到现成的资料,现在自己做出来了,拿出来给有需要的人


void Timer1_PWM_Init(void)
{
    GPIO_InitTypeDef GPIO_InitStructure;
    TIM_TimeBaseInitTypeDef TIM_BaseInitStructure;
    TIM_OCInitTypeDef TIM_OCInitStructure;

    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA|RCC_APB2Periph_AFIO,ENABLE);
    RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
    GPIO_InitStructure.GPIO_Pin=GPIO_Pin_8;
    GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF_PP;
    GPIO_InitStructure.GPIO_Speed=GPIO_Speed_50MHz;
    GPIO_Init(GPIOA, &GPIO_InitStructure);
    //TIM1基本计数器设置(设置PWM频率)
    //频率=TIM1_CLK/(ARR+1)
    TIM_BaseInitStructure.TIM_Period = 1894;            //不分频。PWM频率=72000/1894=38Khz
    TIM_BaseInitStructure.TIM_Prescaler = 0;
    TIM_BaseInitStructure.TIM_ClockDivision = 0;
    TIM_BaseInitStructure.TIM_CounterMode = TIM_CounterMode_Up;
    TIM_BaseInitStructure.TIM_RepetitionCounter = 0;
    TIM_TimeBaseInit(TIM1, &TIM_BaseInitStructure);
    //启用ARR的影子寄存器(直到产生更新事件才更改设置)
    TIM_ARRPreloadConfig(TIM1, ENABLE);
 //TIM1_OC1模块设置(设置1通道占空比)
    TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
    TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
    TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
    TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
    TIM_OC1Init(TIM1, &TIM_OCInitStructure);
    //启用CCR1寄存器的影子寄存器(直到产生更新事件才更改设置)
    TIM_OC1PreloadConfig(TIM1, TIM_OCPreload_Enable);
    TIM_Cmd(TIM1, ENABLE);                //TIM1开启
    //TIM1_OC通道输出PWM(一定要加)
    TIM_CtrlPWMOutputs(TIM1, ENABLE);
    TIM_SetCompare1(TIM1,625);         //设置占空比为1/3
}

下面是简单的发送
void IR_Send(void)
{
    //9ms
    TIM_Cmd(TIM1, ENABLE);
    Delay_nMS(9);
    //4.5ms
    TIM_Cmd(TIM1, DISABLE);
    Delay_nMS(4);
    Delay_nUS(500);
    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);
    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);

    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);
    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);

    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);
    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);

    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);
    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);

    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);
    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);

    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);
    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);

    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);
    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);

    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);
    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);

    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);
    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);

    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);
    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);

    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);
    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);

    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);
    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);

    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);
    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);

    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);
    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);

    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);
    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);

    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);
    //0
    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
    Delay_nUS(565);

    TIM_Cmd(TIM1, ENABLE);
    Delay_nUS(565);
    Delay_nUS(565);
    Delay_nUS(565);
    TIM_Cmd(TIM1, DISABLE);
}

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