TI太给力了:KeyStone™ Multicore DSP+ARM

2019-07-25 15:13发布

66AK2Ex KeyStone™ Multicore DSP+ARM®
66AK2Hx KeyStone™ Multicore DSP+ARM®

http://www.ti.com/lsds/ti/dsp/keystone_arm/66ak2ex/products.page?paramCriteria=no

http://www.ti.com/lsds/ti/dsp/keystone_arm/66ak2hx/products.page?paramCriteria=no

这才对人类文明的贡献。感谢TI的工程师们。
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19条回答
yyplc
2019-07-25 18:03
DSP与ARM的完美结合~,强悍啊
1 66AK2H12/06 Features and Description
1.1 Features
• Eight (66AK2H12) or Four (66AK2H06)
TMS320C66x™ DSP Core Subsystems (C66x
CorePacs), Each With
– Up to 1.2 GHz C66x Fixed/Floating-Point DSP
Cores
› 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
› 19.2 GFlops/Core for Floating Point @ 1.2 GHz
– Memory
› 32K Byte L1P Per CorePac
› 32K Byte L1D Per CorePac
› 1024K Byte Local L2 Per CorePac
• Multicore Shared Memory Controller (MSMC)
– 6 MB MSM SRAM Memory Shared by DSP CorePacs
and ARM CorePac
– Memory Protection Unit for Both MSM SRAM and
DDR3_EMIF
• ARM® Cortex™-A15 MPCore™ Processors Containing
Four (66AK2H12) or Two (66AK2H06) ARM
Cortex-A15 Cores
– Up to 1.4-GHz Cortex-A15 Processor Core Speed
– 4MB L2 Cache Memory Shared by All ARM
CorePacs
– Full Implementation of ARMv7-A Architecture
Instruction Set
– 32KB L1 Instruction Cache and Data Cache per
Cortex-A15 Processor Core
– AMBA 4.0 AXI Coherency Extension (ACE) Master
Port, Connected to MSMC for Low Latency Access
to Shared MSMC SRAM
• Multicore Navigator
– 16k Multi-Purpose Hardware Queues with Queue
Manager
– Packet-Based DMA for Zero-Overhead Transfers
• Network Coprocessor
– Packet Accelerator Enables Support for
› Transport Plane IPsec, GTP-U, SCTP, PDCP
› L2 User Plane PDCP (RoHC, Air Ciphering)
› 1 Gbps Wire Speed Throughput at 1.5 MPackets
Per Second
– Security Accelerator Engine Enables Support for
› IPSec, SRTP, 3GPP and WiMAX Air Interface, and
SSL/TLS Security
› ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC,
CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW
3G, SHA-1, SHA-2 (256-bit Hash), MD5
› Up To 6.4 Gbps IPSec and 3 Gbps Air Ciphering
– Ethernet Subsystem
› Five SGMII Port Switch
• Peripherals
– Four Lanes of SRIO 2.1
› 5 Gbps Operation Per Lane
› Supports Direct I/O, Message Passing
– Two Lanes PCIe Gen2
› Supports Up To 5 GBaud
– TwoHyperLink
› Supports Connections to Other KeyStone
Architecture Devices Providing Resource
Scalability
› Supports  Up  To  50  GBaud
– Five Enhanced Direct Memory Access (EDMA)
Modules
– Two 72-Bit DDR3 Interfaces with Speeds Up To
1600 MHz
– EMIF16  Interface
– USB  3.0
– Two UART Interfaces
– Three I
2
C Interfaces
– 32  GPIO  Pins
– Three SPI Interfaces
– Semaphore Module
– Twenty  64-Bit  Timers
– Five On-Chip PLLs
• Commercial Case Temperature:
– 0°C to 85°C
• Extended Case Tempera

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