用vivado仿真是遇到下面的问题，代码都看了，没有发现异常
目录下的文件也检查过了，也没有异常
感觉像是软件安装有问题，但也找不出哪里的问题

有没有遇到这种情况，怎么解决的？


[USF-XSim-62] 'compile' step failed with error(s) while executing 'D:/Works/FPGA/Xilinx/project_test_1/project_test_1.sim/sim_1/behav/xsim/compile.bat' script. Please check that the file has the correct 'read/write/execute' permissions and the Tcl console output for any other possible errors or warnings.

[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

testbench -->

module simu(
);
// testbench 时钟信号
reg clk = 0;
always #10 clk <= ~clk;
// 输出信号
wire out;
// 调用test模块
test mytest(clk, out);
endmodule

module -->

module test(
input in,
output out
);
assign out = ~in;
endmodule



此帖出自小平头技术问答