FPGA报错，添加了时钟时序，还有这个报错怎么解决

2019-03-25 07:09发布

站内问答 / FPGA
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Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)

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coyoo
2019-03-25 15:25
< / 哪家器件？Xilinx or Altera？

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