vhdl怎么在一个时钟周期内产生多个脉冲

2019-03-25 07:12发布

用vhdl写一个脉冲信号,来驱动步进电机,但是怎么也写不出怎么在一个周期内产生多个脉冲。
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 2018/08/17 13:24:09
-- Design Name:
-- Module Name: motor10000 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity motor10000 is
    Port
        (
           clk:             in std_logic;
           rst:             in std_logic;
           clk_in:          in std_logic;
           pulse:           out std_logic;
           encoder_b_b:     out std_logic;
           cnt:             out std_logic_vector(15 downto 0)
         --  encoderB_A_L:    out std_logic   
         );
end motor10000;
architecture Behavioral of motor10000 is
     signal cnt_temp:std_logic_vector(15 downto 0);
     
begin
     cnt<=cnt_temp;
--------clk----------
process(clk,rst)
begin
     if rst='0'then
       encoder_b_b<='0';
     elsif clk'event and clk='1'then
       encoder_b_b<='1';
     else
       encoder_b_b<='0';
    end if;   
end process;
--------phase----------
process(clk,rst)
begin
     if rst='0'then
        pulse<='0';
     elsif clk'event and clk='1'then
        pulse<='1';
     else
        pulse<='0';
     end if;
end process;
process(clk_in,rst)
begin
     if rst='0'then
        pulse<='0';
     elsif clk_in'event and clk_in='1'then
        pulse<='0';
--     else
--        pulse<='1';
     end if;
end process;
---------counter-------
process(clk,rst)
begin
     if rst='0'then
        cnt_temp<=x"0000";
     elsif clk'event and clk='1'then
        if cnt_temp=x"00ff"then
           cnt_temp<=x"0000";
        else
           cnt_temp<=cnt_temp+'1';
        end if;
     end if;
end process;
end Behavioral;



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