Vivado报错求助!

2019-03-25 07:24发布

[Opt 31-67] Problem: A LUT6 cell in the design is missing a connection on input pin I3, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: u_mig/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_common0/maintenance_request.maint_arb0/maintenance_request.maint_sre_r_lcl_i_1.

[Opt 31-67] Problem: A LUT6 cell in the design is missing a connection on input pin I5, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: u_mig/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_common0/maintenance_request.maint_arb0/maintenance_request.maint_srx_r_lcl_i_1.

[Opt 31-67] Problem: A LUT6 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: u_mig/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/mc0/i___82.

[Opt 31-67] Problem: A LUT5 cell in the design is missing a connection on input pin I4, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: u_mig/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/mc0/i___83.

[Opt 31-67] Problem: A LUT5 cell in the design is missing a connection on input pin I4, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: u_mig/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_common0/i___81_i_2.
由以上可见,它指向的都是我生成的mig的IP核的底层文件,我找了好久都找不到这个引脚在哪儿?请问大大们,这个问题是因为引脚没连导致的吗?如何解决?

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放学后不许跑
2019-03-26 08:16
zxq6 发表于 2017-7-31 21:51
看描述是缺少输入啊,你从提示的思路去看看?

解决了,在Vivado的实现里有个DRC report,里面会告诉哪些地方没连,其实有三个用户请求引脚我映射出来了,官方例子里面是把这三个引脚直接映射成低电平,即‘0‘

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