我是个小白   从网上找的vivado源程序  没有检出错误  但是仿真和综合的时候显示有错误  
综合的时候只显示有错误  但是我没找到怎么看
仿真的时候 显示的错误如图
他让我看xvlog  我也看不懂  具体如下：
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/src/bd/hdmi_in/ipshared/9097/src/mmcme2_drp.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mmcme2_drp
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_processing_system7_0_0/sim/hdmi_in_processing_system7_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_processing_system7_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_v_axi4s_vid_out_0_0/sim/hdmi_in_v_axi4s_vid_out_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_v_axi4s_vid_out_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_v_vid_in_axi4s_0_0/sim/hdmi_in_v_vid_in_axi4s_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_v_vid_in_axi4s_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_xbar_0/sim/hdmi_in_xbar_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_xbar_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_xbar_1/sim/hdmi_in_xbar_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_xbar_1
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_s00_regslice_0/sim/hdmi_in_s00_regslice_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_s00_regslice_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_s01_regslice_0/sim/hdmi_in_s01_regslice_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_s01_regslice_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_m00_data_fifo_0/sim/hdmi_in_m00_data_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_m00_data_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_m00_regslice_0/sim/hdmi_in_m00_regslice_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_m00_regslice_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_auto_pc_0/sim/hdmi_in_auto_pc_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_auto_pc_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_auto_us_df_0/sim/hdmi_in_auto_us_df_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_auto_us_df_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_auto_us_df_1/sim/hdmi_in_auto_us_df_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_auto_us_df_1
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_auto_pc_1/sim/hdmi_in_auto_pc_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_auto_pc_1
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl

求大神帮我看看
此帖出自小平头技术问答