本帖最后由 yyplc 于 2013-8-16 15:24 编辑

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我们公司上新项目需要66A系列的芯片或者C6678的芯片或者DM8168
的芯片（其中基于DM8168产品开发完了）的可靠的代理商，
要求供货稳定，有优势，有技术支持！
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66AK2E05:
Features
CorePac Processors
Quad or single Cortex-A15 processors
One C66x DSP core
Network Coprocessor
Packet coprocessor (IPv4/IPv6) for Layer 2-4
Security coprocessors IPSec/SRTP
Eight-port 1Gb Ethernet switch
Two-port 10Gb Ethernet switch (66AK2E05 only)
Memory
Cache-coherent Multicore Shared Memory Controller (MSMC)
1MB per core Level 2 RAM/cache
2MB shared memory with ECC and cache coherency DDR3/3L 1600 interface with ECC
KeyStone II Architecture
Multicore Navigator; brings single-core programming simplicity to multicore SoCs
8,000 atomic hardware queues
TeraNet - on-chip interconnect providing more than two terabits per second throughput
Low power - 6-9 Watts at 55°C case temperature
High speed I/O
PCI Express Gen2-up to 10 Gbps
USB 3.0
HyperLink - up to 50 Gbaud for chip-to-chip interconnect

C6678:
Features
Eight TMS320C66x DSP Core Subsystems at 1.00 GHz and 1.25GHz
320 GMAC/160 GFLOP @ 1.25GHz
32KB L1P, 32KB L1D, 512KB L2 Per Core
4MB Shared L2
Multicore Navigator and TeraNet Switch Fabric - 2 Tb
Network Coprocessors- Packet Accelerator, Security Accelerator
Four Lanes of SRIO 2.1 - 5 Gbaud Per Lane Full Duplex
Two Lanes PCIe Gen2 - 5 Gbaud Per Lane Full Duplex
HyperLink - 50Gbaud Operation, Full Duplex
Ethernet MAC Subsystem - Two SGMII Ports w/ 10/100/1000 Mbps operation
64-Bit DDR3 Interface (DDR3-1600) - 8 GByte Addressable Memory Space
16-Bit EMIF - Async SRAM, NAND and NOR Flash Support
Two Telecom Serial Ports (TSIP) - 2/4/8 Lanes at 32.768/16.384/8.192
UART Interface
I2C Interface
16 GPIO Pins
SPI Interface
Sixteen 64-Bit Timers
Three On-Chip PLLs

DM8168:
Features
High-Performance DaVinci Video Processors
ARM® Cortex-A8 RISC Processor
Up to 1.35 GHz
C674x VLIW DSP
Up to 1.125 GHz
Up to 9000 MIPS and 6750 MFLOPS
Fully Software-Compatible with C67x+™ and C64x+™
ARM Cortex™-A8 Core
ARMv7 Architecture
In-Order, Dual-Issue, Superscalar Processor Core
NEON Multimedia Architecture
Supports Integer and Floating Point (VFPv3-IEEE754 compliant)
Jazelle RCT Execution Environment
ARM® Cortex™-A8 Memory Architecture
32K-Byte Instruction and Data Caches
256K-Byte L2 Cache
64K-Byte RAM, 48K-Byte Boot ROM
TMS320C674x Floating-Point VLIW DSP
64 General-Purpose Registers (32-Bit)
Six ALU (32-Bit and 40-Bit) Functional Units
Supports 32-Bit Integer, SP (IEEE Single Precision, 32-Bit) and DP (IEEE Double Precision, 64-Bit) Floating Point
Supports 32-Bit Integer, SP (IEEE Single Precision, 32-Bit) and DP (IEEE Double Precision, 64-Bit) Floating Point
Supports up to Four SP Adds Per Clock and Four DP Adds Every Two Clocks
Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle
Two Multiply Functional Units
Mixed-Precision IEEE Floating-Point Multiply Supported up to:
2 SP x SP → SP Per Clock
2 SP x SP → DP Every Two Clocks
2 SP x DP → DP Every Three Clocks
2 DP x DP → DP Every Four Clocks
Fixed-Point Multiply Supports Two 32 x 32 Multiplies, Four 16 x 16-bit Multiplies including Complex Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle
C674x Two-Level Memory Architecture
32K-Byte L1P and L1D RAM and Cache
256K-Byte L2 Unified Mapped RAM and Caches
System Memory Management Unit (System MMU)
Maps C674x DSP and EMDA TCB Memory Accesses to System Addresses
512K-Bytes On-Chip Memory Controller (OCMC) RAM
Media Controller
Manages HDVPSS and HDVICP2 modules
Up to Three Programmable High-Definition Video Image Coprocessing (HDVICP2) Engines
Encode, Decode, Transcode Operations
H.264, MPEG2, VC1, MPEG4 SP and ASP
SGX530 3D Graphics Engine (available only on the DM8168 and DM8166 device)
Delivers up to 30 MTriangles per second
Universal Scalable Shader Engine
Direct3D Mobile, OpenGL ES 1.1 and 2.0, OpenVG 1.1, OpenMax API Support
Advanced Geometry DMA Driven Operation
Programmable HQ Image Anti-Aliasing
Endianness
ARM, DSP Instructions and Data – Little Endian
HD Video Processing Subsystem (HDVPSS)
Two 165 MHz HD Video Capture Channels
One 16-Bit or 24-Bit and One 16-Bit Channel
Each Channel Splittable Into Dual 8-Bit Capture Channels
Two 165 MHz HD Video Display Channels
One 16-Bit, 24-Bit, 30-Bit Channel and One 16-bit Channel
Simultaneous SD and HD Analog Output
Digital HDMI 1.3 transmitter with PHY with HDCP up to 165-MHz pixel clock
Three Graphics Layers
Dual 32-Bit DDR2 and DDR3 SDRAM Interfaces
Supports up to DDR2-800 and DDR3-1600
Up to Eight x8 Devices Total
2 GB Total Address Space
Dynamic Memory Manager (DMM)
Programmable Multi-Zone Memory Mapping and Interleaving
Enables Efficient 2D Block Accesses
Supports Tiled Objects in 0°, 90°, 180°, or 270 Orientation and Mirroring
Optimizes Interlaced Accesses
One PCI Express (PCIe®) 2.0 Port With Integrated PHY
Single Port With 1 or 2 Lanes at 5.0 GT per second
Configurable as Root Complex or Endpoint
Serial ATA (SATA) 3.0 Gbps Controller With Integrated PHYs
Direct Interface for Two Hard Disk Drives
Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries
Supports Port Multiplier and Command-Based Switching
Two 10 Mbps, 100 Mbps, and 1000 Mbps Ethernet MACs (EMAC)
IEEE 802.3 Compliant (3.3V IO Only)
MII and GMII Media Independent Interfaces
Management Data IO (MDIO) Module
Dual USB 2.0 Ports With Integrated PHYs
USB 2.0 High-Speed and Full-Speed Client
USB 2.0 High-Speed, Full-Speed, and Low-Speed Host
Supports End Points 0-15
General Purpose Memory Controller (GPMC)
8-Bit and 16-Bit Multiplexed Address and Data Bus
Up to 6 Chip Selects With up to 256M-Byte Address Space per Chip Select Pin
Glueless Interface to NOR Flash, NAND Flash (With BCH and Hamming Error Code Detection), SRAM and Pseudo-SRAM
Error Locator Module (ELM) Outside of GPMC to Provide Up to 16-Bit and 512-Bytes Hardware ECC for NAND
Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs
Enhanced Direct-Memory-Access (EDMA) Controller
Four Transfer Controllers
64 Independent DMA Channels and 8 QDMA Channels
Seven 32-Bit General-Purpose Timers
One System Watchdog Timer
Three Configurable UART, IrDA, and CIR Modules
UART0 With Modem Control Signals
Supports up to 3.6864 Mbps UART
SIR, MIR, FIR (4.0 MBAUD), and CIR
One 40-MHz Serial Peripheral Interface (SPI) With Four Chip-Selects
SD and SDIO Serial Interface (1-Bit and 4-Bit)
Dual Inter-Integrated Circuit (I2C BUS) Ports
Three Multichannel Audio Serial Ports
One Six-Serializer Transmit and Receive Port
Two Dual-Serializer Transmit and Receive Ports
DIT-Capable For SDIF and PDIF (All Ports)
Multichannel Buffered Serial Port (McBSP)
Transmit and Receive Clocks up to 48 MHz
Two Clock Zones and Two Serial Data Pins
Supports TDM, I2S, and Similar Formats
Real-Time Clock (RTC)
One-Time or Periodic Interrupt Generation
Up to 64 General-Purpose IO (GPIO) Pins
On-Chip ARM® ROM Bootloader (RBL)
Power, Reset, and Clock Management
SmartReflex Technology (Level 2)
Seven Independent Core Power Domains
Clock Enable and Disable Control For Subsystems and Peripherals
IEEE-1149.1 (JTAG) and IEEE-1149.7 (cJTAG) Compatible
1031-Pin Pb-Free BGA Package (CYG Suffix), 0.65-mm Ball Pitch
Via Channel™ Technology Enables use of 0.8-mm Design Rules
40-nm CMOS Technology
3.3-V Single-Ended LVCMOS IOs (except for DDR3 at 1.5 V, DDR2 at 1.8 V, and DEV_CLKIN at 1.8 V)

Cortex, NEON are trademarks of ARM Ltd or its subsidiaries.
ARM, Jazelle, Thumb are registered trademarks of ARM Ltd or its subsidiaries.
USSE, POWERVR are trademarks of Imagination Technologies Limited.
OpenVG, OpenMax are trademarks of Khronos Group Inc.
Direct3D, Microsoft, Windows are registered trademarks of Microsoft Corporation in the United States and/or other countries.
I2C BUS is a registered trademark of NXP B.V. Corporation Netherlands.
PCI Express, PCIe are registered trademarks of PCI-SIG.
OpenGL is a registered trademark of Silicon Graphics International Corp. or its subsidiaries in the United States and/or other countries.
All other trademarks are the property of their respective owners.