本帖最后由 1520415739 于 2016-11-6 23:31 编辑
这是跑马灯的Verilog,不知道是不是有问题,出不了结果,大家帮忙看看,如果没错麻烦帮忙写一下测试代码,谢谢了!
module ledrun(clk, q, rst);//模块名(端口1,端口2,端口3)
input clk, rst;//clk脉冲信号,rst复位信号
output[15:0] q;//输出16盏灯
reg[15:0] q;
reg[15:0] counter;
reg[2:0] state, next_state;
reg[3:0] count;
parameter
state0=3'b000,
state1=3'b001,
state2=3'b011,
state3=3'b010,
state4=3'b110,
state5=3'b111,
state6=3'b101,
state7=3'b100;//状态常量
always@(posedge clk)//下降沿触发
begin
if(rst)
begin
state=state0;
q=16'b0000000000000000;//把q全置零
end
else
begin
state=next_state;
end
case(state)
state0://从左到右奇数顺序亮
begin
if(q==16'b0000000000000000)
begin
q='b1000000000000000;
end
else
begin
if(count=='b0111)
begin
count=0;
q='b0000000000000010;
next_state=state1;
end
else
begin
q=q>>2;
count=count+1;
next_state=state0;
end
end
end
state1://从右到左奇数灯顺序亮
begin
if(count=='b0111)
begin
count=0;
q='b1000000000000010;
next_state=state2;
end
else
begin
q=q<<2;
count=count+1;
next_state=state1;
end
end
state2://从两边到中间奇数灯顺序亮
begin
if(count=='b0011)
begin
count=0;
q='b0000001010000000;
next_state=state3;
end
else
begin
q[15:9]=q[15:9]>>2;
q[7:1]=q[7:1]<<2;
count=count+1;
next_state=state2;
end
end
state3://从中间到两边奇数灯顺序亮
begin
if(count=='b0011)
begin
count=0;
q='b0100000000000000;
next_state=state4;
end
else
begin
q[15:9]=q[15:9]<<2;
q[7:1]=q[7:1]>>2;
count=count+1;
next_state=state3;
end
end
state4://从左到右偶数顺序亮
begin
if(count=='b0111)
begin
count=0;
q='b0000000000000001;
next_state=state5;
end
else
begin
q=q>>2;
count=count+1;
next_state=state4;
end
end
state5://从右到左偶数顺序亮
begin
if(count=='b0111)
begin
count=0;
q='b0000000101000000;
next_state=state6;
end
else
begin
q=q<<2;
count=count+1;
next_state=state5;
end
end
state6://从两边往中间偶数顺序亮
begin
if(count=='b0011)
begin
count=0;
q='b0100000000000001;
next_state=state7;
end
else
begin
q[6:0]=q[6:0]>>2;
q[14:8]=q[14:8]<<2;
count=count+1;
next_state=state6;
end
end
state7://从中间往两边偶数顺序亮
begin
if(count=='b0011)
begin
count=0;
q='b1000000000000000;
next_state=state0;
end
else
begin
q[6:0]=q[6:0]<<2;
q[14:7]=q[14:7]>>2;
count=count+1;
next_state=state7;
end
end
endcase
end
endmodule
此帖出自
小平头技术问答
2.还是状态机的第一段,时序逻辑请使用 <= ;
3.推荐使用三段式状态机写法,便于维护;
4.状态机第二段,状态控制和输出控制在一起,太长看不完。。。排版也怪怪的,如果以上说的无效,可能是第二段的逻辑上有问题,粗看一遍就这些
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