各位大神，为什么我编的并串转换后会在每一个并行数据之间有一个低电平的无效数据。always@(posedge clk or negedge rst)begin if(!rst) begin count<=0; clkdiv<=0; end else begin count<=count+1; if(count==9) clkdiv<=~clkdiv; else if(count==19) begin clkdiv<=~clkdiv; count<=0; end endend
always@(posedge clk or negedge rst)begin if(!rst) begin pscen<=0; sdata<=0; state<=16; data_buf<=0; end else begin case(state) 16: begin pscen<=0; sdata<=0; data_buf<=data_in; state<=15; end 15: begin pscen<=1; sdata<=data_buf[15]; state<=14; end 14: begin pscen<=1; sdata<=data_buf[14]; state<=13; end 13: begin pscen<=1; sdata<=data_buf[13]; state<=12; end 12: begin pscen<=1; sdata<=data_buf[12]; state<=11; end 11: begin pscen<=1; sdata<=data_buf[11]; state<=10; end 10: begin pscen<=1; sdata<=data_buf[10]; state<=9; end 9: begin pscen<=1; sdata<=data_buf[9]; state<=8; end 8: begin pscen<=1; sdata<=data_buf[8]; state<=7; end 7: begin pscen<=1; sdata<=data_buf[7]; state<=6; end 6: begin pscen<=1; sdata<=data_buf[6]; state<=5; end 5: begin pscen<=1; sdata<=data_buf[5]; state<=4; end 4: begin pscen<=1; sdata<=data_buf[4]; state<=3; end 3: begin pscen<=1; sdata<=data_buf[3]; state<=2; end 2: begin pscen<=1; sdata<=data_buf[2]; state<=1; end 1: begin pscen<=1; sdata<=data_buf[1]; state<=0; end 0: begin pscen<=1; sdata<=data_buf[0]; state<=16; end default: begin pscen<=0; sdata<=0; state<=16; end endcase endend


仿真图 此帖出自小平头技术问答