RT,
module Divider_verilog(
clk, rst_n, fm
);
input clk; //时钟信号,50MHz
input rst_n; //复位信号,低电平有效
output fm; //蜂鸣器,0--响,1--不响
assign fm = 1'b0;
reg[5:0] cnt;
always @(posedge clk or negedge rst_n)
if(!rst_n)
cnt <= 6'd0;
else if(cnt < 6'd49)
cnt <= cnt + 1'b1;
else
cnt <= 6'd0;
assign fm = (cnt <= 6'd24) ? 1'b0:1'b1;
endmodule
出现了这么多错误!= =
Error (10028): Can't resolve multiple constant drivers for net "fm" at Divider_verilog.v(21)
Error (10029): Constant driver at Divider_verilog.v(9)
Error (12153): Can't elaborate top-level user hierarchy
Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings
一模一样的程序啊,对了我用的EP4CE6E22C8N这个芯片
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