求大神FPGA整合模块菜鸟加新手不会弄，播放模块 Library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity music is generic(mid8:integer range 1000 to 4000:= 1911; mid9:integer range 1000 to 4000:= 1703; mid10:integer range 1000 to 4000:= 1517;mid11:integer range 1000 to 4000:= 1432;mid12:integer range 1000 to 4000:= 1276;mid13:integer range 1000 to 4000:= 1137;mid14:integer range 1000 to 4000:= 1012;low1:integer range 1000 to 4000:= 3823;low2:integer range 1000 to 4000:= 3405;low3:integer range 1000 to 4000:= 3034;low4:integer range 1000 to 4000:= 2863;low5:integer range 1000 to 4000:= 2551;low6:integer range 1000 to 4000:= 2273; low7:integer range 1000 to 4000:= 2025; high15:integer range 100 to 4000:= 956;high16:integer range 100 to 4000:=851; high17:integer range 100 to 4000:= 758;high18:integer range 100 to 4000:= 716;high19:integer range 100 to 4000:= 638; high20:integer range 100 to 4000:= 568;high21:integer range 100 to 4000:= 506);port(clk:in std_logic; start:in std_logic;out_sound1:out std_logic; sel:in std_logic;choose:in std_logic_vector(0 to 1);seg6:out std_logic_vector(0 to 6)    ); end music;architecture behav of music is signal clk_4Hz : std_logic; signal clk_1MHz : std_logic;signal count : integer range 0 to 4096;signal freq : integer range 0 to 4096; signal counter : integer range 0 to 150; signal max_250000 : std_logic_vector(17 downto 0); signal tmp:integer range 0 to 100;signal rset:std_logic;signal out_sound12:std_logic; signal out_sound11:std_logic;signal max_50 : std_logic_vector(5 downto 0); begin process(start,clk)beginif start='0'then clk_1MHz<='0';max_50 <= "000000";elsif clk'event and clk='1' then if max_50>= "110001"thenmax_50<="000000";else max_50<=max_50+1;end if;if max_50="000000"then clk_1MHz<='1';else clk_1MHz<='0'; end if; end if; end process;process(start,clk_1MHz) begin if start='0'then clk_4Hz<='0'; max_250000<="000000000000000000";elsif clk_1MHz'event and clk_1MHz='1' then if max_250000>= "111101000010001111"then max_250000<="000000000000000000"; else max_250000<=max_250000+1; end if; if max_250000="000000000000000000"then clk_4Hz<='1'; else clk_4Hz<='0'; end if;end if;  end process;process(choose,clk)--选歌信号检测进程variable a:std_logic_vector(0 to 1);variable b:std_logic_vector(0 to 1);variable c:std_logic_vector(0 to 1);beginif clk'event and clk='1' then b:=a;a:=choose; c:= b - a;end if; if c="00" then rset<='0';else rset<='1';end if;end process;process(clk_4Hz,rset,start,choose)beginif  start='0' then tmp<=0;elsif rset='1' then tmp<=0;elsif (clk_4Hz'event and clk_4Hz='1') then if tmp>=56 then tmp<=0; else tmp<=tmp+1; end if;end if;case choose is when "01" => counter<=tmp;seg6<="1111001";when "10" => counter<=tmp+57;seg6<="0100100";when others => counter<=0;seg6<="1000000";end case; end process;process(counter)begincase counter is when 0=>freq<=0;when 1=>freq<=mid10;when 2=>freq<=mid10;when 3=>freq<=mid11;when 4=>freq<=mid12;when 5=>freq<=mid12;when 6=>freq<=mid8;when 7=>freq<=mid9;when 8=>freq<=mid10;when 9=>freq<=mid10;when 10=>freq<=mid10;when 11=>freq<=mid11;when 12=>freq<=mid12;when 13=>freq<=mid12;when 14=>freq<=mid9;when 15=>freq<=mid10;when 16=>freq<=mid11;when 17=>freq<=mid11;when 18=>freq<=mid11;when 19=>freq<=mid10;when 20=>freq<=mid8;when 21=>freq<=mid8;when 22=>freq<=mid11;when 23=>freq<=mid10;when 24=>freq<=mid11;when 25=>freq<=mid11;when 26=>freq<=low6;when 27=>freq<=mid8;when 28=>freq<=mid9;when 29=>freq<=mid9;when 30=>freq<=mid8;when 31=>freq<=mid9;when 32=>freq<=mid10; when 33=>freq<=mid10;when 34=>freq<=mid10;when 35=>freq<=mid11;when 36=>freq<=mid12;when 37=>freq<=mid12;when 38=>freq<=mid13;when 39=>freq<=mid14;when 40=>freq<=high15;when 41=>freq<=high15;when 42=>freq<=mid10;when 43=>freq<=mid11;when 44=>freq<=mid12;when 45=>freq<=mid12;when 46=>freq<=mid9;when 47=>freq<=mid10;when 48=>freq<=mid11;when 49=>freq<=mid10;when 50=>freq<=mid11;when 51=>freq<=high15;when 52=>freq<=high15;when 53=>freq<=high15;when 54=>freq<=mid9;when 55=>freq<=mid10;when 56=>freq<=mid11;when 57=>freq<=high15;when 58=>freq<=mid10;when 59=>freq<=mid10;when 60=>freq<=mid10;when 61=>freq<=mid9;when 62=>freq<=mid10; when 63=>freq<=0;when 64=>freq<=0;when 65=>freq<=0;when 66=>freq<=mid10;when 67=>freq<=mid12;when 68=>freq<=mid10;when 69=>freq<=mid9;when 70=>freq<=mid10;when 71=>freq<=mid10;when 72=>freq<=mid10;when 73=>freq<=mid10;when 74=>freq<=mid8;when 75=>freq<=mid8;when 76=>freq<=mid8;when 77=>freq<=mid9;when 78=>freq<=mid10; when 79=>freq<=mid12;when 80=>freq<=mid10;when 81=>freq<=mid10;when 82=>freq<=mid9;when 83=>freq<=mid9;when 84=>freq<=mid9;when 85=>freq<=mid8;when 86=>freq<=mid9;when 87=>freq<=mid9;when 88=>freq<=mid9;when 89=>freq<=mid9;when 90=>freq<=mid10;when 91=>freq<=mid10;when 92=>freq<=mid10;when 93=>freq<=mid12;when 94=>freq<=mid13;when 95=>freq<=mid12;when 96=>freq<=mid12;when 97=>freq<=mid12;when 98=>freq<=mid13;when 99=>freq<=mid12;when 100=>freq<=mid12;when 101=>freq<=mid10;when 102=>freq<=mid12;when 103=>freq<=mid12;when 104=>freq<=mid12;when 105=>freq<=low5;when 106=>freq<=mid10;when 107=>freq<=mid10;when 108=>freq<=mid9;when 109=>freq<=mid9;when 110=>freq<=mid12;when 111=>freq<=mid12;when 112=>freq<=mid10;when 113=>freq<=mid9;when others=>freq<=0;end case;end process;   process(clk_1MHz,start,sel)   begin   if sel='0'then out_sound12<='0';  else    if start='0'then  count<=0;     out_sound12<='0';        elsif clk_1MHz'event and clk_1MHz='1'then   if freq=0 then out_sound12<='0';           elsif count=0 then              count<=freq;             out_sound12<='1';    elsecount<=count-1;    out_sound12<='0'; end if; end if;    end if; end process;PROCESS(out_sound12)   --二分颁，方波输出 BEGIN    IF out_sound12 'EVENT AND out_sound12='1' THEN        out_sound11 <=NOT out_sound11;    END IF;     out_sound1<=out_sound11; END PROCESS;    end behav; 顶层模块Library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity top isport (clk0:in std_logic; start0:in std_logic; sel0:in std_logic;kbcol0:in std_logic_vector(0 to 3);kbrow0:out std_logic_vector(0 to 3); out_sound0:out std_logic;seg60:out std_logic_vector(0 to 6); choose0:in std_logic_vector(0 to 1));end;architecture one of top is component music port(clk:in std_logic; start:in std_logic; out_sound1:out std_logic; sel:in std_logic; choose:in std_logic_vector(0 to 1); seg6:out std_logic_vector(0 to 6));end component; component pianoport (clk,start:in std_logic; kbcol:in std_logic_vector(0 to 3);kbrow:out std_logic_vector(0 to 3); out_sound2:out std_logic; sel:in std_logic);end component; component or22port(a,b:in std_logic; c:out std_logic); end component; signal g,h:std_logic; begin u1:music port map(clk=>clk0,start=>start0,choose=>choose0,sel=>sel0,out_sound1=>g,seg6=>seg60); u2:piano port map(kbcol=>kbcol0,kbrow=>kbrow0,clk=>clk0,sel=>sel0,start=>start0, out_sound2=>h);u3: or22 port map(a=>g,b=>h,c=>out_sound0);end; 弹奏模块Library ieee; use ieee.std_logic_1164.all;  use ieee.std_logic_arith.all;   use ieee.std_logic_unsigned.all;      entity piano is  port (clk,start:in std_logic;        kbcol:in std_logic_vector(0 to 3);           kbrow:out std_logic_vector(0 to 3);             out_sound2:out std_logic;               sel:in std_logic    );             end entity;               architecture piano of piano is  signal state:std_logic_vector(2 downto 0);  signal clk1:std_logic;               signal clk_1MHz : std_logic;              signal d:std_logic_vector(4 downto 0);              signal snote:std_logic_vector(4 downto 0);              signal sscal:std_logic_vector(1 downto 0);               signal cnt,scnt:std_logic_vector(9 downto 0);               signal ctrln:std_logic_vector(2 downto 0);               signal count,freq:integer range 0 to 4096;                signal  out_sound22:std_logic;                signal  out_sound21:std_logic;                  signal d0,d1,d2,d3,d_reg:std_logic_vector(4 downto 0);                 signal max_50 : std_logic_vector(5 downto 0);                 constant low1:integer:=3822;                     constant low2:integer:=3405;                  constant low3:integer:=3034;                  constant low4:integer:=2863;                  constant low5:integer:=2551;                   constant low6:integer:=2273;                   constant low7:integer:=2025;                    constant mid1:integer:=1911;                     constant mid2:integer:=1703;                    constant mid3:integer:=1517;                     constant mid4:integer:=1432;                     constant mid5:integer:=1276;                      constant mid6:integer:=1137;                     constant mid7:integer:=1012;                      constant high1:integer:=956;                      constant high2:integer:=851;                       constant high3:integer:=758;                        constant high4:integer:=716;                         constant high5:integer:=638;                          constant high6:integer:=568;                           constant high7:integer:=506;                          constant stop:integer:=0;                          begin                             process(start,clk) begin                                if start='0'then                                        clk_1MHz<='0';         max_50 <= "000000";                                        elsif clk'event and clk='1' then                                          if max_50>= "110001"then          max_50<="000000";      else max_50<=max_50+1;                                          end if;                                           if max_50="000000"then          clk_1MHz<='1';      else clk_1MHz<='0';end if;    end if; end process;   clk1<=cnt(9);  process(clk_1MHz)   begin    if clk_1MHz'event and clk_1MHz='1'then cnt<=cnt+1;    end if;     end process;    d<=d0 or d1 or d2 or d3;process(clk1) begin  if clk1'event and clk1='1'then case state is    when "000"=>kbrow<="1110";state<="001";    case kbcol iswhen"0111"=>d0<="11111";         when"1011"=>d0<="11011";          when"1101"=>d0<="10111";        when"1110"=>d0<="10011";         when others=>d0<="00000";      end case;   when"001"=>kbrow<="1101";state<="010";   case kbcol is            when"0111"=>d1<="11110";          when"1011"=>d1<="11010";           when"1101"=>d1<="10110";          when"1110"=>d1<="10010";           when others=>d1<="00000";    end case;    when"010"=>kbrow<="1011";state<="011";     case kbcol is            when"0111"=>d2<="11101";           when"1011"=>d2<="11001";          when"1101"=>d2<="10101";            when"1110"=>d2<="10001";             when others=>d2<="00000";    end case;   when"011"=>kbrow<="0111";state<="100";     case kbcol is           when"0111"=>d3<="11100";            when"1011"=>d3<="11000";           when"1101"=>d3<="10100";           when"1110"=>d3<="10000";           when others=>d3<="00000";    end case;    when"100"=>state<="000";       if d="00000"then            d_reg<=d;          if scnt=100 then          snote<="00000";          else          scnt<=scnt+1;         end if;      else           scnt<="0000000000";             if d /= d_reg then                    d_reg<=d;             if d>="10001"and d<="10111"then                snote<=sscal&d(2 downto 0);          elsif d="11010"then           sscal<="11";                      elsif d="11011"then           sscal<="10";                            elsif d="11100"then           sscal<="01";                             end if;                                 end if;                                     end if;                                     when others=>state<="000";                                     end case;                                             -- end if;                                       end if;  end process;      process(snote)  begin    case snote is         when"01001"=>freq<=low1;        when"01010"=>freq<=low2;        when"01011"=>freq<=low3;        when"01100"=>freq<=low4;        when"01101"=>freq<=low5;        when"01110"=>freq<=low6;        when"01111"=>freq<=low7;        when"10001"=>freq<=mid1;       when"10010"=>freq<=mid2;       when"10011"=>freq<=mid3;       when"10100"=>freq<=mid4;        when"10101"=>freq<=mid5;        when"10110"=>freq<=mid6;        when"10111"=>freq<=mid7;       when"11001"=>freq<=high1;       when"11010"=>freq<=high2;        when"11011"=>freq<=high3;        when"11100"=>freq<=high4;       when"11101"=>freq<=high5;        when"11110"=>freq<=high6;       when"11111"=>freq<=high7;       when others=>freq<=stop;      end case; end process;    process(clk_1MHz,sel,start) begin                                                       if sel='1'or start='0'then out_sound22<='0';                                           else                                               if clk_1MHz'event and clk_1MHz='1'then                                                 if freq=0 then out_sound22 <='0';                                                 elsif count=0then               count<=freq;                out_sound22<='1';                                                    else                count<=count-1;               out_sound22<='0';             end if;                                                 end if;                                               end if;                                        end process;                                                 PROCESS(out_sound22)                                           BEGIN    IF out_sound22 'EVENT AND out_sound22='1' THEN      out_sound21 <=NOT out_sound21;   END IF;    out_sound2<=out_sound21;                                           END PROCESS;                                            end piano;                                      
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