这是我的代码: module VGA(clk,rst_n,vgar,vgab,vgag,vga_vs,vga_hs) ;
input clk,rst_n; //50Mhz
output [3:0] vgar;
output [3:0] vgag;
output [3:0] vgab;
output vga_vs;
output vga_hs;
reg [10:0]ths ; //行坐标,11位计数器,计数Ta+Tb+Tc+Td+Te+Tf+Tg=96+40+8+640+8+8=800;
//Ta,Tb,Tc,Td,Te,Tf,Tg分别为
reg [9:0]tvs ;//列坐标,10位计数器,计数Ta+Tb+Tc+Td+Te+Tf+Tg=2+25+8+480+8+2=525
/*--------行扫描计数--------------------**/
always @(posedge clk or negedge rst_n)
if(!rst_n) ths<=11'd0;
else if(ths==11'd1039) ths<=11'd0;
else if(ths<11'd1039) ths<=ths+11'd1;
/*--------列扫描计数--------------------**/
always @(posedge clk or negedge rst_n)
if(!rst_n) tvs<=10'd0;
else if(tvs==10'd665) tvs<=10'd0;
else if(ths==11'd1039) tvs<=tvs+10'd1;
/*---------------------------------------*/
/*--------------VGA时序产生模块---------------*/
reg hsync;
reg vsync;
always @(posedge clk or negedge rst_n)
if(!rst_n) hsync<=1'b1;
else if(ths==11'd0) hsync<=1'b0;
else if(ths==11'd120) hsync<=1'b1 ; //此处可能为hsync<=10'h3ff
always @(posedge clk or negedge rst_n)
if(!rst_n) vsync<=1'b1;
else if(tvs==10'd0) vsync<=1'b0;
else if(ths==10'd6) vsync<=1'b1;
assign vga_hs=hsync;
assign vga_vs=vsync;
/*------显示模块--------*/
/*------确定显示位置模块--------*/
wire [10:0]hs_pos; //hsync的位置
wire [9:0]vs_pos; //vsync的位置
wire valid; //有效显示区域
assign valid=(tvs>187)&&(tvs<987)&&(ths>31)&&(ths<631); //确定显示区域
assign hs_pos=ths-11'd187;
assign vs_pos=tvs-10'd31;
/*----------显示--------------*/
//显示一个矩形框
wire a_dis,b_dis,c_dis,d_dis;
assign a_dis=(vs_pos>=324)&&(vs_pos<=354)&&(hs_pos>=268)&&(hs_pos<=568);
assign b_dis=(vs_pos>=624)&&(vs_pos<=644)&&(hs_pos>=268)&&(hs_pos<=568);
assign c_dis=(vs_pos>=354)&&(vs_pos<=624)&&(hs_pos>=268)&&(hs_pos<=298);
assign d_dis=(vs_pos>=354)&&(vs_pos<=624)&&(hs_pos>=538)&&(hs_pos<=568);
//reg [11:0] vga_rgb;
reg [3:0] vga_r;
reg [3:0] vga_g;
reg [3:0] vga_b;
always @(posedge clk )
if(!valid) begin vga_r<=0;vga_g<=0;vga_b<=0;end //vga_rgb<=9'd0;
else if(valid==(a_dis|b_dis|c_dis|d_dis)) begin vga_r<=15;vga_g<=15;vga_b<=15;end //vga_rgb<=9'd500;
else begin vga_r<=8;vga_g<=8;vga_b<=8;end //vga_rgb<=9'd138;
assign vgar= vga_r ;
assign vgag= vga_g ;
assign vgab= vga_b;
//assign vgar=vga_rgb[11:8];
//assign vgag=vga_rgb[7:4];
//assign vgab=vga_rgb[3:0];
endmodule
此帖出自
小平头技术问答
Critical Warning (332148): Timing requirements not met
一周热门 更多>