USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CONTROL IS
          PORT(S2,S1,S0: STD_LOGIC_VECTOR(3 DOWNTO 0);
                    CLK:IN STD_LOGIC;
      L1,L2,L3,R1,R2,R3:OUT STD_LOGIC);
END ENTITY CONTROL; 
            ARCHITECTURE CTRL OF CONTROL IS
            BEGIN
            PROCESS(S2,S1,S0,CLK)
            BEGIN
              IF(S2="0" AND S1="0" AND S0="0")THEN
              L1<='0';L2<='0';L3<='0';
              R1<='0';R2<='0';R3<='0';
            ELSIF CLK'EVENT AND CLK='1' THEN
             IF(S2="0" AND S1="0" AND S0="1")THEN
              L1<='1';L2<='0';L3<='0';
              R1<='0';R2<='0';R3<='0';
            ELSIF(S2="0" AND S1="1" AND S0="0")THEN
              L1<='0';L2<='0';L3<='0';
              R1<='1';R2<='0';R3<='0';
           END IF;
          END IF;
         END  PROCESS;
            PROCESS(S2,S1,S0)
            BEGIN
              IF(S2="0" AND S1="1" AND S0="1")THEN
              L1<='1';L2<='1';L3<='1';
              R1<='1';R2<='1';R3<='1';
           ELSIF(S2="1" AND S1="0" AND S0="0")THEN
              L1<='0';L2<='0';L3<='1';
              R1<='0';R2<='0';R3<='1';
           END IF;
         END  PROCESS;
       END  ARCHITECTURE CTRL;
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