LPC1768 UCOSIII 无法进定时tim0中断-xia

LPC1768 UCOSIII 无法进定时tim0中断

2019-08-17 00:46发布

4条回答

2019-08-17 05:26

本帖最后由 xia_yangchun 于 2017-7-13 21:42 编辑

已经解决，发现是在UCOSIII的BSP_Init()初始化时钟后，我加入的初始化GPIO，UART，Timer后有个中断向量表的初始化和关闭中断函数，把中断关掉了，我把Timer_Config();调整到CSP_IntInit();和 CSP_IntDisAll(CSP_INT_CTRL_NBR_MAIN);的后面后可以正常进入中断，输出中断的调试信息了。
原子哥帮忙看看，常规的是不是要把所有的GPIO，UART。Timer，SPI等等的外设初始化都移至CSP_IntDisAll(CSP_INT_CTRL_NBR_MAIN);的后面去。

[mw_shl_code=c,true]*                                           BSP_Init()
*
* Description : Initialize the Board Support Package (BSP).
*
* Argument(s) : none.
*
* Return(s) : none.
*
* Caller(s) : Application.
*
* Note(s)    : (1) The PLL0 Frequency is determined by:
*
*                      Fcco = (2 x M x Fin) / N
*
*                      where M = PLL0 Multipler
*                            N = PLL0 Pre-dividier
*                         Fin  = PLL0 Input Frequency (Main oscillator).
*
*             (2) PLL0 settings must meet the following:
*                      Fin is in the range of 32Khz to 50 Mhz.
*                      Fcco is in the range of 275 Mhz to 550 Mhz
*
*             (3) The LPC17xx CPU frequency is determined by:
*
*                      CPU_freq = Fcc0 / CPU_Div
*
*             (4) The USB clock frequency is determined by:
*
*                      USB_Clk = M x Fosc x P, or USB_clk = Fcco / (2 x P)
*
*                      Fcco =  Fosc x 2 x M x 2 x P
*
*                      where Fcco = PLL1 output frequency.
*                            M = PLL1 multiplier.
*                            P = PLL1 pre-divider.
*                            Fosc = Oscialltor  frequency.
*
*             (5) The PLL1 inputs and settings must meet the following criteria:
*                Fosc is in the range of 10 Mhz to 25 Mhz.
*                USBClk  is 48 Mhz
*                Fcco is in the range of 156 Mhz to 320 Mhz
*
*             (6) In this example the LPC1768 operates:
*
*                      PLL0_Fcco = 2 x 25 x 12 / 2
*                      PLL0_Fcco = 300mhz
*
*                      CPU_freq  =  300 Mhz  / 3
*                               =  100 Mhz
*
*                      PLL1_Fcc0 = 12 x 4 x 2 x 2 = 192 Mhz.
*                      USB_Clk = 12 x 4       =  48 Mhz.
*********************************************************************************************************
*/

void  BSP_Init (void)
{
CPU_INT16U reg_to;
CPU_INT32U reg_val;
CPU_SR_ALLOC();

                                                            /* ---------------- CLOCK INITIALIZATION -------------- */
BSP_REG_FLASHCFG = BSP_MSK_FLASHCFG_CLK_6                /* Set 6 cycles to acces the Flash memory.             */
                  | BSP_MSK_FLASHCFG_RST_VAL;
                                                            /* ----------- MAIN OSCILLATOR INITIALIZATION --------- */
DEF_BIT_CLR(BSP_REG_SCS, BSP_BIT_SCS_OSCRANGE);          /* Set the main oscillator range                      */

reg_to = BSP_VAL_MAX_TO;

DEF_BIT_SET(BSP_REG_SCS, BSP_BIT_SCS_OSCEN);             /* Enable the Main Oscillator                         */

                                                            /* Wait until the main oscillator is enabled.          */
while (DEF_BIT_IS_CLR(BSP_REG_SCS, BSP_BIT_SCS_OSCSTAT) &&
      (reg_to > 0u)) {
      reg_to--;
}

if (reg_to == 0u) {                                        /* Configuration fail                                  */
      return;
}

BSP_REG_PCLKSEL0 = DEF_BIT_NONE;                         /* All peripheral clock runrs at CPU_Clk / 4 = 25 Mhz */
BSP_REG_PCLKSEL1 = DEF_BIT_NONE;

                                                            /* ------------------ PLL0 CONFIGURATION -------------- */

reg_val  = (((25u - 1u) <<  0u) & BSP_MSK_PLLCFG0_MSEL)    /* PLL0 values M = 25 & N = 2 (see note #6)          */
         | ((( 2u - 1u) << 16u) & BSP_MSK_PLLCFG0_NSEL);
                                                            /* 1. Disconnect PLL0 with one feed sequence if PLL ... */
                                                            /* ... already connected.                            */
if (DEF_BIT_IS_SET(BSP_REG_PLLSTAT(0u), BSP_BIT_PLLSTAT_PLLC0_STAT)) {
      DEF_BIT_CLR(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLC);
      BSP_PLL_FEED_SEQ(0u);
}

DEF_BIT_CLR(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLE);    /* 2. Disable PLL0 with one feed sequence             */
BSP_PLL_FEED_SEQ(0u);

BSP_REG_CCLKCFG = (1u - 1u);                            /* 3. Change the CPU clock divider setting to speed ... */
                                                            /* ... operation without PLL0                         */

BSP_REG_CLKSRCSEL = BSP_BIT_CLKSRCSEL_MAIN;                /* 4. Select the main osc. as the PLL0 clock source    */

BSP_REG_PLLCFG(0u) = reg_val;                            /* 5. Write to the PLLCFG and make it effective with... */
BSP_PLL_FEED_SEQ(0u)                                     /* ... one one feed sequence                         */

DEF_BIT_SET(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLE);    /* 6. Enable PLL0 with one feed sequence             */
BSP_PLL_FEED_SEQ(0u);

BSP_REG_CCLKCFG = (3u - 1u);                            /* 7. Change the CPU clock divider setting for ...    */
                                                            /* ... operation with PLL0                            */

reg_to = BSP_VAL_MAX_TO;                                  /* 8. Wait for PLL0 to achieve lock by monitoring ... */
                                                            /* ... the PLOCK0 bit in the PLL0STAT                */
while (DEF_BIT_IS_CLR(BSP_REG_PLLSTAT(0u), BSP_BIT_PLLSTAT_PLOCK0) &&
      (reg_to > 0u)) {
      reg_to--;
}

if (reg_to == 0u) {
      return;
}

DEF_BIT_SET(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLC);    /* 9. Connect PLL0 with one feed sequence             */
BSP_PLL_FEED_SEQ(0u);
                                                            /* ------------------ PLL1 CONFIGURATION -------------- */
reg_val  = (((4u - 1u)  <<  0u) & BSP_MSK_PLLCFG1_MSEL)    /* PLL1 values M = 4; P = 2 coded as '01' (see note #6) */
         | (((0x01u ) <<  5u) & BSP_MSK_PLLCFG1_NSEL);

DEF_BIT_CLR(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLC);    /* 1. Disconnect PLL1 with one feed sequence          */
BSP_PLL_FEED_SEQ(1u);

DEF_BIT_CLR(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLE);    /* 2. Disable PLL1 with one feed sequence             */
BSP_PLL_FEED_SEQ(1u);

BSP_REG_PLLCFG(1u) = reg_val;                            /* 3. Write to the PLLCFG and make it effective with... */
BSP_PLL_FEED_SEQ(1u);                                     /* ... one one feed sequence                         */

DEF_BIT_SET(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLE);    /* 4. Enable PLL1 with one feed sequence             */
BSP_PLL_FEED_SEQ(1u);

reg_to = BSP_VAL_MAX_TO;                                  /* 5. Wait for PLL1 to achieve lock by monitoring ... */
                                                            /* ... the PLOCK1 bit in the PLL1STAT                */
while (DEF_BIT_IS_CLR(BSP_REG_PLLSTAT(1u), BSP_BIT_PLLSTAT_PLOCK1) &&
      (reg_to > 0u)) {
      reg_to--;
}

if (reg_to == 0u) {
      return;
}

DEF_BIT_SET(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLC);    /* 6. Connect PLL1 with one feed sequence             */
BSP_PLL_FEED_SEQ(1u);

BSP_REG_FLASHCFG = BSP_MSK_FLASHCFG_CLK_5                /* Set 5 cycles to acces the Flash memory.             */
                  | BSP_MSK_FLASHCFG_RST_VAL;

//初始化GPIO,时钟
            GPIO_Config();
//       UART0_DebugConfig();
            debug_frmwrk_init();//PC串口 UART0初始化

            //NetDevice_Config();//配置设备的IP、网关、子网掩码、MAC地址等参数
            UART3_Config();
            Timer_Config();
CSP_IntInit();
CSP_IntDisAll(CSP_INT_CTRL_NBR_MAIN);


}

[/mw_shl_code]

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