module tribuffer (a,b,en,dr);
inout[7:0]a,b;
input en,dr;
reg [7:0]a,b;
always@(*)
  if(dr==1)
   a=en?b:8'bz;
  else
   b=en?a:8'bz;
endmodule
为什么会有以下warning
Warning (10240): Verilog HDL Always Construct warning at tribuffer.v(6): inferring latch(es) for variable "a", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at tribuffer.v(6): inferring latch(es) for variable "b", which holds its previous value in one or more paths through the always construct 此帖出自小平头技术问答