module bianma(in,EI,EO,GS,out);
input [7:0] in;
input EI;
output EO,GS;
output [2:0]out;
reg [2:0]out;
reg EO,GS;
always @(EI,in)
if(EI)
case(in)
  8'b11111110: begin out=3'b111;GS=0;EO=1;end
  8'b1111110x: begin out=3'b110;GS=0;EO=1;end
  8'b111110xx: begin out=3'b101;GS=0;EO=1;end
  8'b11110xxx: begin out=3'b100;GS=0;EO=1;end
  8'b1110xxxx: begin out=3'b011;GS=0;EO=1;end
  8'b110xxxxx: begin out=3'b101;GS=0;EO=1;end
  8'b10xxxxxx: begin out=3'b110;GS=0;EO=1;end
  8'b0xxxxxxx: begin out=3'b111;GS=0;EO=1;end
  8'b11111111: begin out=3'b111;GS=1;EO=0;end
endcase
else
  begin
  out=3'b111;
  GS=1;EO=1;
  end
endmodule
以上是一个三线八线优先编码器的verilog代码求高手给指点一下为什么会有以下警告：
Warning (10240): Verilog HDL Always Construct warning at bianma.v(8): inferring latch(es) for variable "out", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at bianma.v(8): inferring latch(es) for variable "GS", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at bianma.v(8): inferring latch(es) for variable "EO", which holds its previous value in one or more paths through the always construct
万分感谢 此帖出自小平头技术问答