这是我的程序，sram的读写时序控制。
module RTL_SRAM
(
sysclk,
rst_b,
out_addre,//address bus
in_data,
out_data,
in_address,
data_bus,//data bus
iowb,
iorb,
w_flag_r,
r_flag_r,
//out_en,
data_ready
);
//=================================================================================================
//Input and output declaration
//=================================================================================================
input sysclk;
input rst_b;
input w_flag_r;
input r_flag_r;
output [4:0] out_addre; //5  address lines
output data_ready;
input [4:0] in_address;
input [7:0] in_data;
output [7:0] out_data;
inout [7:0] data_bus;
output iowb;
output iorb;
//output out_en;
//=================================================================================================
//Wire and reg declaration
//=================================================================================================
wire sysclk;
wire rst_b;
wire iowb;
wire iorb;
wire data_ready;
wire [4:0] out_addre;
reg [7:0] data_bus_r;
wire [7:0] data_bus;
wire w_flag_r;
wire r_flag_r;
wire [4:0] in_address;
wire [7:0] in_data;
wire [7:0] out_data;
//wire [7:0] data_bus;
//=================================================================================================
//wire and reg in the module
//=================================================================================================
reg [7:0] out_data_r;
reg [4:0] out_addre_r; //5  address lines
//wire [7:0] data_bus;    //8 data lines
reg iowb_r;
reg iorb_r;
reg data_ready_r;
//reg [1:0] delay_cnt;
//reg [1:0] delay_cnt_n;
reg [3:0] w_state;
reg [3:0] r_state;
reg [1:0] state_ctl;
reg [1:0] state_ctl_n;
reg out_en;
//w_state
parameter step_0 = 4'd0;
parameter step_1 = 4'd1;
parameter step_2 = 4'd2;
parameter step_3 = 4'd3;
parameter step_4 = 4'd4;
parameter step_5 = 4'd5;
parameter step_6 = 4'd6;
//r_state
parameter step_a = 4'd7;
parameter step_b = 4'd8;
parameter step_c = 4'd9;
parameter step_d = 4'd10;
parameter step_e = 4'd11;
parameter step_f = 4'd12;
parameter step_g = 4'd13;
//state
parameter IDLE = 2'd0;
parameter W_STATE = 2'd1;
parameter R_STATE = 2'd2;
//=================================================================================================
//Logic
//=================================================================================================
always @ (posedge sysclk or negedge rst_b)
begin
if(!rst_b)
  state_ctl <= IDLE;
else
  state_ctl <= state_ctl_n;
end
always @ (*)
begin
if(!rst_b)
  begin
   state_ctl_n <= IDLE;
   out_en <= 1'b0;
  end
else
  case(state_ctl)
   IDLE:
    if(w_flag_r)
     begin
      state_ctl_n <= W_STATE;
      w_state <= step_0;
     end
    else if(r_flag_r)
     begin
      state_ctl_n <= R_STATE;
      r_state <= step_a;
     end
    else
     begin
      state_ctl_n <= IDLE;
      out_en <= 1'b0;
     end
   W_STATE:
    case(w_state)
     
     step_0:
      begin
       iowb_r <= 1'b1;
       out_addre_r <= in_address;
       w_state <= step_1;
      end
     step_1:
      begin
       iowb_r <= 1'b0;//read enable
       w_state <= step_2;
      end
     step_2:
      begin
       data_bus_r <= in_data;
       out_en <= 1'b1;
       w_state <= step_3;
      end
     step_3:
      w_state <= step_4;
     step_4:
      w_state <= step_5;
     step_5:
      begin
       iowb_r <= 1'b1;
       w_state <= step_6;
      end
     step_6:
      begin
       w_state <= IDLE;
       out_en <= 1'b0;
      end
     default:
      begin
       w_state <= IDLE;
       out_en <= 1'b0;
      end
    endcase
   R_STATE:
    case(r_state)
     step_a:
      begin
       iorb_r <= 1'b1;
       out_addre_r <= in_address;
       r_state <= step_b;
      end
     step_b:
      begin
       iorb_r <= 1'b0;//read enable
       r_state <= step_c;
      end
     step_c:
      r_state <= step_d;
     step_d:
      r_state <= step_e;
     step_e:
      begin
       out_data_r <= data_bus;////
       data_ready_r <= 1'b1;
       r_state <= step_f;
      end
     step_f:
      begin
       iorb_r <= 1'b1;
       data_ready_r <= 1'b0;
       r_state <= step_g;
      end
     step_g:
      begin
       r_state <= IDLE;
       out_en <= 1'b0;
      end
     default:
      begin
       r_state <= IDLE;
       out_en <= 1'b0;
      end
    endcase   
  endcase
end
assign iowb = iowb_r;
assign iorb = iorb_r;
assign data_ready = data_ready_r;
assign out_addre = out_addre_r;
assign out_data = out_data_r;
//assign data_bus_in = data_bus;
assign data_bus = (out_en) ? data_bus_r : 8'hzz;
//assign data_bus_out = data_bus_r;
endmodule


出现了下面的警告：
  Warning (10240): Verilog HDL Always Construct warning at RTL_SRAM.v(107): inferring latch(es) for variable "state_ctl_n", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at RTL_SRAM.v(107): inferring latch(es) for variable "out_en", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at RTL_SRAM.v(107): inferring latch(es) for variable "w_state", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at RTL_SRAM.v(107): inferring latch(es) for variable "r_state", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at RTL_SRAM.v(107): inferring latch(es) for variable "iowb_r", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at RTL_SRAM.v(107): inferring latch(es) for variable "out_addre_r", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at RTL_SRAM.v(107): inferring latch(es) for variable "data_bus_r", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at RTL_SRAM.v(107): inferring latch(es) for variable "iorb_r", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at RTL_SRAM.v(107): inferring latch(es) for variable "out_data_r", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at RTL_SRAM.v(107): inferring latch(es) for variable "data_ready_r", which holds its previous value in one or more paths through the always construct

该怎么解决？？求指导！ 此帖出自小平头技术问答