我用了Altera的EP1C6Q240C8的一块学习板，自己用VHDL编了个小程序：library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt is
  port (clk,rst:in std_logic;
        count:out std_logic);
end entity;
architecture behv of cnt is
 type state is (s1,s2);
 signal stx:state;
 signal fuck:std_logic_vector(3 downto 0);
 signal q:std_logic;
  begin
   com1:process(clk,rst)
          begin
           if rst='1' then stx<=s1;
            elsif clk='1' and clk'event then
             case stx is
              when s1=> fuck<=fuck+1;if fuck<8 then q<='0';stx<=s1;
                        else stx<=s2;end if;
              when s2=> if fuck>0 then fuck<=fuck-1; q<='1';stx<=s2;
                        else stx<=s1;end if;
             end case;
            end if;
           end process;
   com2:process(fuck)
         begin
          if fuck=9 then count<='1';
          else count<='0';
          end if;
         end process;
  end behv;
  我想在板子上实现，请问下，程序里的clk应该配置在哪个引脚，本菜鸟对FPGA里面的时钟感到混乱，不知道是内部是否有时钟输出，不知道每次程序里面的clk应该配置在哪个引脚上才能够在板子上实现输出脉冲。。。急急急 谢谢大侠们  
    此帖出自小平头技术问答