module  sec (clk,seg,dig);
input clk ;
output[7:0]seg,dig;
reg [7:0]seg,dig,date;
reg [32:0]count ;
reg clk1k;
reg[3:0]s_1,s_2,cnt;



always@(clk)
begin
if (count=='d10000)
begin  count<=0;
clk1k<=~clk1k;
end
else  
count<=count+1;
end


always@(clk1k)
if (s_1==4'd9)
begin
s_1<=0;
if (s_2==4'd5)
s_2<=0;
else
begin
cnt<='d1;
s_2<=s_2+1;
end
end
else begin
s_1<=s_1+1;
cnt<='d0;
end
always@(clk1k)
begin
case(cnt)
4'd0:begin dig<=8'b011111111;date<=s_1;end
4'd1:begin dig<=8'b101111111;date<=s_2;end
endcase
end
always@(date)
begin
case(date)
4'd0:seg=8'hc0;
4'd1:seg=8'hf9;
4'd2:seg=8'ha4;
4'd3:seg=8'hb0;
4'd4:seg=8'h99;
4'd5:seg=8'h92;
4'd6:seg=8'h82;
4'd7:seg=8'hf8;
4'd8:seg=8'h80;
4'd9:seg=8'h90;
endcase
end  
endmodule 此帖出自小平头技术问答