今天编译工程发现以下warning，找了很久也没有解决方法，不知道有人遇到吗？ ①Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details 这个我查了报告说是：missingdrive strength and slew rate 网上找了很久都没有发现怎么解决。
②Warning: 5 pins must meet Altera requirements for 3.3, 3.0, and 2.5-V interfaces. Refer to the device Application Note 447 (Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems).
 Info: Pin SID0 uses I/O standard 3.3-V LVTTL at AB10
 Info: Pin E1_NUM[1] uses I/O standard 3.3-V LVTTL at Y10
 Info: Pin E1_NUM[0] uses I/O standard 3.3-V LVTTL at K22
 Info: Pin C16 uses I/O standard 3.3-V LVTTL at AA11
 Info: Pin F16 uses I/O standard 3.3-V LVTTL at AB11 不知道这两个会不会影响很大呢？ 此帖出自小平头技术问答