求dac8668的verilog驱动代码,最好是用zynq—7000平台可以用的

2019-11-21 13:42发布

<font size="4">我需要同时驱动两路da&nbsp;&nbsp;因为这个da8568上有两个模拟输出A,B<br> 希望大神帮我解决&nbsp; &nbsp; 球球你们&nbsp; &nbsp;技术手册已上传&nbsp; &nbsp; </font><br> <br><p> 另外&nbsp;&nbsp;我自己拙劣代码&nbsp; &nbsp;也给大神们看看&nbsp;</p><pre style="max-width: 100%;"><code class="cpp hljs" codemark="1">`timescale <span class="hljs-number">1</span>ns / <span class="hljs-number">1</span><span class="hljs-function">ps module <span class="hljs-title">da</span><span class="hljs-params">( input clk,<span class="hljs-comment">//125M的时钟!!!</span> input rst_n, output sclk,<span class="hljs-comment">//为50M 所以周期20ns</span> output cs_n,<span class="hljs-comment">////输出通道 就是那个sync</span> output reg clr_n,<span class="hljs-comment">//接高电平 这样处理</span> output reg load_n,<span class="hljs-comment">///ci此程序定义的那个接地 同步不需要管</span> output din, <span class="hljs-comment">//input [15:0] reg1,</span> <span class="hljs-comment">//input [15:0] reg2,</span> output reg LED )</span></span>; wire clk1; wire [<span class="hljs-number">15</span>:<span class="hljs-number">0</span>] reg1,reg2; <span class="hljs-comment">//四个变量用了一个</span> <span class="hljs-comment">//parameter CMD_SOFT_RST = 32'h1FFF_FFFF;//0001 11XX XXXX XXXX XXXX XXXX XXXX XXXX</span> <span class="hljs-comment">//parameter CMD_POWER_ON = 32'h090A0000;</span> parameter CMD_WRITE_INPUT_REG = <span class="hljs-number">32</span><span class="hljs-string">'h00000000; //parameter CMD_LOAD = 32'</span>h060000FF;<span class="hljs-comment">//32'h060000FF0000 0110 0000000000 涓嶅 鏀逛笅; 0000 0110 0000 0000 0000 0000 1111 1111</span> wire [<span class="hljs-number">15</span>:<span class="hljs-number">0</span>]DA1buff; wire [<span class="hljs-number">15</span>:<span class="hljs-number">0</span>]DA2buff; reg [<span class="hljs-number">31</span>:<span class="hljs-number">0</span>]PSbuff; reg [<span class="hljs-number">12</span>:<span class="hljs-number">0</span>]dacnt; <span class="hljs-comment">//max=4095</span> reg xdaccsf; wire xdaccsb; wire we1,we2; <span class="hljs-function">clk_wiz_0 <span class="hljs-title">q</span> <span class="hljs-params">( <span class="hljs-comment">// clock out ports</span> .clk_out1(sclk)</span>, .<span class="hljs-title">clk_out2</span><span class="hljs-params">(clk1)</span>, <span class="hljs-comment">// output clk_out1</span> <span class="hljs-comment">// Status and control signals</span> .<span class="hljs-title">reset</span><span class="hljs-params">(rst_n)</span>, <span class="hljs-comment">// input reset</span> <span class="hljs-comment">// Clock in ports</span> .<span class="hljs-title">clk_in1</span><span class="hljs-params">( clk)</span>)</span>; <span class="hljs-function">wave_gen <span class="hljs-title">a</span><span class="hljs-params">( .clk1(clk1)</span>, .<span class="hljs-title">rst_n</span><span class="hljs-params">(rst_n)</span>, .<span class="hljs-title">reg1</span><span class="hljs-params">(reg1)</span>, .<span class="hljs-title">reg2</span><span class="hljs-params">(reg2)</span> )</span>; <span class="hljs-comment">// DAC8568 是32位寄存器,写一次寄存器需要32个sclk </span> assign we1 = (dacnt == <span class="hljs-number">12</span><span class="hljs-string">'d1) ? 1'</span>b1 : <span class="hljs-number">1</span><span class="hljs-string">'b0; //we1 cnt 1 + 32 = 33 assign we2 = (dacnt == 12'</span>d38) ? <span class="hljs-number">1</span><span class="hljs-string">'b1 : 1'</span>b0; <span class="hljs-comment">//we2 cnt 38 + 32 = 70</span> assign xdaccsb = (dacnt &gt; <span class="hljs-number">12</span><span class="hljs-string">'d0 &amp;&amp; dacnt &lt; 12'</span>d33) ? <span class="hljs-number">1</span><span class="hljs-string">'b0 : //片选? 给100ns转换时间 (dacnt &gt; 12'</span>d38 &amp;&amp; dacnt &lt; <span class="hljs-number">12</span><span class="hljs-string">'d71) ? 1'</span>b0 : <span class="hljs-number">1</span>; assign DA1buff = reg1; <span class="hljs-comment">//12'h555;//12'hFFF - DA1 ; </span> assign DA2buff = reg2; <span class="hljs-comment">//12'hAAA;//12'hFFF - DA2 ;</span> <span class="hljs-comment">//assign sclk = clk;</span> assign cs_n = xdaccsf; assign din = PSbuff[<span class="hljs-number">31</span>]; <span class="hljs-comment">//assign clr_n = 1'b1;</span> always @(posedge sclk or negedge rst_n) <span class="hljs-function">begin <span class="hljs-title">IF</span> <span class="hljs-params">(rst_n)</span> begin xdaccsf &lt;</span>= <span class="hljs-number">1</span><span class="hljs-string">'b1; led&lt;=1'</span>b0; end <span class="hljs-keyword">else</span> begin xdaccsf &lt;= xdaccsb; led&lt;=<span class="hljs-number">1</span><span class="hljs-string">'b1; end end always @(posedge sclk or negedge rst_n) begin if (rst_n) begin clr_n=1'</span>b1; load_n=<span class="hljs-number">1</span><span class="hljs-string">'b0; dacnt &lt;= 12'</span>d0; PSbuff &lt;= <span class="hljs-number">32</span><span class="hljs-string">'h00000000; end else if( dacnt==12'</span>d72) <span class="hljs-comment">// 澶嶄綅鍚庣涓?涓懆鏈熻繘琛屽垵濮嬪寲 daenable 浣胯兘 </span> dacnt &lt;= <span class="hljs-number">12</span><span class="hljs-string">'d0; else begin clr_n=1'</span>b1; load_n=<span class="hljs-number">1</span><span class="hljs-string">'b0; dacnt &lt;= dacnt+1'</span>d1; <span class="hljs-keyword">if</span> (we1) PSbuff &lt;= CMD_WRITE_INPUT_REG | <span class="hljs-number">0</span>&lt;&lt;<span class="hljs-number">20</span> | DA1buff &lt;&lt; <span class="hljs-number">4</span>; <span class="hljs-comment">//因为后四位没用 无关的 移动是因为地址在动</span> <span class="hljs-keyword">else</span> <span class="hljs-keyword">if</span> (we2) PSbuff &lt;= CMD_WRITE_INPUT_REG | <span class="hljs-number">1</span>&lt;&lt;<span class="hljs-number">20</span> | DA2buff &lt;&lt; <span class="hljs-number">4</span>; <span class="hljs-keyword">else</span> PSbuff &lt;= {PSbuff[<span class="hljs-number">30</span>:<span class="hljs-number">0</span>],<span class="hljs-number">1</span><span class="hljs-string">'bZ}; //默认高阻态 end end endmodule `timescale 1ns / 1ps module wave_gen( clk1, rst_n,reg1,reg2 ); parameter c=16'</span>d655; input clk1, rst_n; output [<span class="hljs-number">15</span>:<span class="hljs-number">0</span>] reg1, reg2; reg [<span class="hljs-number">15</span>:<span class="hljs-number">0</span>] y=<span class="hljs-number">1</span><span class="hljs-string">'b1; reg [15:0] cnt =1'</span>b1; reg [<span class="hljs-number">15</span>:<span class="hljs-number">0</span>] cnt1 =<span class="hljs-number">1</span><span class="hljs-string">'b0; reg[15:0] reg1,reg2; always @(posedge clk1 or negedge rst_n) begin if (rst_n) begin cnt1 &lt;= 12'</span>d0; cnt &lt;= <span class="hljs-number">12</span><span class="hljs-string">'d1; end else if(cnt1==12'</span>d72) <span class="hljs-comment">// 澶嶄綅鍚庣涓?涓懆鏈熻繘琛屽垵濮嬪寲 daenable 浣胯兘 </span> begin cnt1 &lt;= <span class="hljs-number">12</span><span class="hljs-string">'d0; cnt&lt;=cnt+1; y&lt;=c*cnt; end else if (cnt==100) cnt&lt;=1; else begin cnt1 &lt;= cnt1+1'</span>d1; reg1&lt;=y; reg2&lt;=y; end end <span class="hljs-comment">// always @(posedge clk or negedge rst_n) begin</span> <span class="hljs-comment">// if(rst_n)</span> <span class="hljs-comment">// begin</span> <span class="hljs-comment">// cnt1&lt;=12'd0;</span> <span class="hljs-comment">// end</span> <span class="hljs-comment">// else </span> <span class="hljs-comment">// begin</span> <span class="hljs-comment">// reg1&lt;=y;</span> <span class="hljs-comment">// reg2&lt;=y;</span> <span class="hljs-comment">// end; </span> <span class="hljs-comment">// end</span> endmodule[/size]</code></pre><p><br></p><dl class="tattl"> </dl> <p><br></p><p></p><p><br></p>
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