<pre style="max-width: 100%;"><code class="cpp hljs" codemark="1"><span class="hljs-function">module <span class="hljs-title">LED1</span><span class="hljs-params">(clk,rst,led)</span></span>; input clk,rst; output led; parameter time_1 = <span class="hljs-number">27</span><span class="hljs-string">'d5000_0000; reg[26:0] cnt; reg led; always @(posedge clk or negedge rst) IF(!rst) cnt &lt;= 27'</span>d0; <span class="hljs-keyword">else</span> <span class="hljs-keyword">if</span>(cnt == time_1) cnt &lt;= <span class="hljs-number">27</span><span class="hljs-string">'d0; else cnt &lt;= cnt + 1'</span>b1; always @(posedge clk or negedge rst) <span class="hljs-keyword">if</span>(!rst) led &lt;= <span class="hljs-number">1</span><span class="hljs-string">'b1; else if(cnt == time_1) led &lt;= ~led; endmodule `timescale 1 ns/ 1 ns module led1_vlg_tst(); reg eachvec; reg clk; reg rst; reg cnt; wire led; led1 i1 ( .clk(clk), .led(led), .rst(rst) ); initial begin clk = 0; rst = 0; #100 rst = 1; end always #1 clk = ~clk; endmodule cnt 一直为 x 不计数</span></code></pre> <ignore_js_op> <dl class="tattl attm"> <dd> <img src="data/attach/1911/xmhdfm67j7wce79hjmvvtmq8efrr0wlh.png" alt="QQ图片20190923155543.png" title="QQ图片20190923155543.png"> </dd> </dl> </ignore_js_op> <p><br></p>