LIBRARY IEEE;                                                 
USE IEEE.STD_LOGIC_1164.ALL;                    
USE IEEE.std_logic_unsigned.ALL; ENTITY Vhdl1 IS
    PORT
    (
  L,R,M:IN STD_LOGIC;
  Input: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
  Output: OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
    );
END Vhdl1; ARCHITECTURE test OF Vhdl1 IS      
BEGIN                                                                 mainProcess:process (L,R,M,Input)
  if M='0' then
  Output<=Input;
  else
  Output<="1111111111111111";
  end if;
  end process;
  
END test;   以上代码在EPM240中输出的不是稳定的3.3V，  而是脉冲，而且很容易被干扰，崩溃中！！！！！ 此帖出自小平头技术问答