STM32

开贴记录SWD 脱机烧录器开发过程，请各路大神指教

2019-12-09 19:23发布

站内问答 / STM32/STM8
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参考 CMISI_DAP,BlackMagic代码。
预备下周末结案，目前方案：
1：Host用STM32F427，跑RTEMS系统， IO口模拟SWD时序。
2：flash的操作函数，由Host通过SWD下载入target ram执行。（CMISI_DAP采用这种方式）
     不知道jlink的flash操作是不是一样的原理。他要适用这么多芯片，那得有准备多少这样的小程序啊。。。
3：USB用的虚拟串口，用ST官方提供的驱动，上位机编程简单。tafget本身程序.bin文件由上位机通过虚拟串口传入。
     此虚拟串口的波特率，奇偶，起停位设置均形同虚设。

目前状态：
SWD时序基本调试通过，读写target ID/reg已经正常，暂时未经过高强度测试。。
正在弄flash操作。
友情提示: 此问题已得到解决，问题已经关闭,关闭后问题禁止继续编辑，回答。
94条回答
shangdawei
2019-12-11 09:32
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Freescale OSBDM JM60仿真器OSBDM Development Port Interfaces
BGND Interface
The BGND interface provides the standard 6 pin connection for the single wire BGND signal type development port.Target types that apply this development port are the 9S08, RS08, and Coldfire V1.+V_TRG, TBGND, TRG_RST*, and Ground are applied by this port type.The BGND interface applies U4 as the signal transceiver.U4 is a 74LVC1T45 logic gate with voltage level shifting features.Operation on the target side (+V_TRG) is 1.8V to 5.5V.The JM60 side is always +5V from the +5V_SW signal.
JM60 signals TBGND_EN, TBGND_IN, and TBGND_OUT provide the communication and control for this interface.
All these signals are associated with JM60 timer channels for precise timing capability to a 41.67ns time step period.For more information on the input and output ports, refer to the Signal Chart section.
TBGND_ EN provides directional control for transmit or receive operations.The signal is logic high for transmit output and logic low to receive input.JM60 timer 2 channel 1 provides the primary signal direction control during the communication with the target.The idle condition is low so that the interface is not driven unless the communication is intended.During the communication, the direction is fixed to output the command to the target.During the reception, the signal is timed in edge aligned PWM mode to provide the BGND start pulse prior to the target reply input.
TBGND_OUT provides the transmit signal output from the JM60 to the target.Timer 2 channel 0 controls this signal in edge aligned PWM mode.For data transmission, the timer channel will output an active low signal with a time period that represents a logic one bit value or logic 0 bit value.In receive mode, the timer channel will provide a low output for the start bit on the BGND signal and then provide timing internally for the reply signal input time window.
TBGND_IN provides receive signal input from the target to the JM60.Timer 1 channel 3 is applied to measure the input signal duration in capture mode (25Mhz BDC clock maximum).This operation provides the timing to determine a logic 1 or 0 bit value input from the target.RS08 type targets apply a lower speed communication technique that inputs the JM60 port value (sample mode) instead of using the timer capture.This is due to the RS08 will not provide a stable input signal after the start bit generation and creates false timer capture edges.Other undefined target types may exhibit the same issue and may apply sample mode, if required (10MHz BDC clock maximum).NOTE The TBGND_OUT and TBGND_IN signals are connected with resistor R1. R1 provides isolation between the 2 timer channels.


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