library IEEE;
use IEEE.STD_LOGIC_1164.ALL; entity period_1ms is
 port (
  CLKIN : in std_logic;
  CLR : in std_logic;
  LOAD : in std_logic; 
     DATA : in std_logic_vector(15 downto 0);
  CLKOUT : out std_logic
 );
end entity;
library IEEE;
use IEEE.std_logic_unsigned.all; architecture beh of period_1ms is
 signal TC_S : std_logic:='0';
 signal TEMP_Q : std_logic_vector(15 downto 0):=x"1F3F";   --默认实时周期为1ms
 signal count  : std_logic_vector(15 downto 0):=x"1F3F";   begin
 
 process(CLKIN,DATA,CLR,LOAD)--可设定实时周期的大小
 begin
   if CLR = '0' then
    TEMP_Q <= x"1F3F";
   else 
  if rising_edge( CLKIN) then 
     if LOAD = '0' then
   TEMP_Q <= DATA;
        end if;
  end if;
   end if;
 end process;
 
 process( CLKIN, CLR,TEMP_Q,TC_S)
 begin
  if CLR = '0' then   
   count <= TEMP_Q ;
   TC_S <='0';
   
  elsif rising_edge( CLKIN) then
    if  count = x"0000" then
     count <= TEMP_Q;
     TC_S <= NOT TC_S;
    else
     count <= count-1;
    end if;
   end if;
 end process;  CLKOUT<=  TC_S;  end architecture; [ 本帖最后由 purpleshellfish 于 2012-2-13 15:25 编辑 ] 此帖出自小平头技术问答