< / 这是my_state源程序：（显示0-9）
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity my_state is
port (        clk: in std_logic;
                flow_out:out std_logic;
                show:out std_logic_vector(3 downto 0));
               
                end;               
architecture one of my_state is
type mystate is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10);
signal current_state,next_state :mystate;
begin
process (clk)
begin
flow_out<='0';
case current_state is
when s0=> show<="0000";next_state<=s1;
when s1=> show<="0001";next_state<=s2;
when s2=> show<="0010";next_state<=s3;
when s3=> show<="0011";next_state<=s4;
when s4=> show<="0100";next_state<=s5;
when s5=> show<="0101";next_state<=s6;
when s6=> show<="0110";next_state<=s7;
when s7=> show<="0111";next_state<=s8;
when s8=> show<="1000";next_state<=s9;
when s9=> show<="1001";next_state<=s10;
when s10=> show<="0000";next_state<=s1;flow_out<='1';

end case;
end process;


process(clk)
begin
if clk'event and clk='1' then
current_state<=next_state;
end if;
end process;

end;