Virtex5 mgt 仿真遇到的问题

2019-03-25 09:51发布

站内问答 / FPGA
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各位好  我在用modelsim se 6.5 仿真 rocket io的时候 在modelsim中出现如下警告 ：   # ** Error:  Input Error : RST on instance   must be asserted for 3 CLKIN clock cycles.
#    Time: 19252 ps  Iteration: 4  Instance: /example_tb/example_mgt_top_i/txoutclk_dcm0_i/clock_divider_i/dcm_adv_inst
# ** Error:  Input Error : RST on instance   must be asserted for 3 CLKIN clock cycles.
#    Time: 134452 ps  Iteration: 4  Instance: /example_tb/example_mgt_top_i/txoutclk_dcm0_i/clock_divider_i/dcm_adv_inst   我是将生成ipcore中的仿真代码加入到ise下的工程中，再调用modelsim仿真的。ise下的仿真库我全部编译过。   请问大家这是什么原因造成的？ 此帖出自小平头技术问答
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2条回答
arrow623
2019-03-25 17:38
< / In simulation, the TXOUTCLK port of the MGT will only start toggling 1 or 2 cycles prior to PLLLKDET asserting. If PLLLKDET is used to drive the RST port of the DCM, this can lead to the above warning. In most cases this warning can be ignored, though in rare cases the DCM output will remain flat lined. To work around this possibility, adding a 3-cycle pipeline to PLLLKDET will add enough delay to correctly reset the DCM.

In hardware, this is not a problem as TXOUTCLK will be toggling at the correct speed for a large number of cycles prior to PLLLKDET asserting.

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