小程序求教

2019-03-25 09:53发布

站内问答 / FPGA
13625 18 1248
module count4(clk,reset,out);
  input clk,reset;
  output [3:0]out;
  reg [3:0]out;
  wire clk,reset;
  always @(posedge clk)
  begin
         if(reset)  out<=4'b0000;
         else out<=out+4'b0001;
  end
endmodule //'include "count4.v"; module count4_tp;
  reg clk,reset;
  wire out;
  parameter DELY=200;
  initial #DELY clk=0;
  initial #DELY reset=0;
  count4 mycount(.clk(clk),.reset(reset),.out(out));
  always #DELY clk=~clk;
endmodule 为什么out没有输出啊??? 还有就是 为什么'include 这个不能用？用的时候有这样的错误提示：* Error: E:/Wordspace/work/count4/count4_tp.v(1): near "'i": Illegal base specifier in numeric constant.
** Error: E:/Wordspace/work/count4/count4_tp.v(1): near "'i": syntax error, unexpected "BASE", expecting "class" 求高手指教！！！
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18条回答
leomeng
2019-03-26 20:23
module count(reset,clk,out);
  input clk,reset;
  output out;
  reg [3:0] out;
  initial out=4'b0000;
  always @(posedge clk)
  begin
         if (reset) out<=4'b0000;
         else out<=out+4'b0001;
end
endmodule
‘timescale 1ns/1ns
‘define DEL 50
‘include "./count.v"
module count_tb;
  reg clk,reset;
  wire [3:0] out;
  parameter DELY=100;
  always #DELY clk=~clk;
  initial #'DEL reset=1'b0;
  initial #'DEL clk=1'b0;
  count count_tb(.reset(reset),.clk(clk),.out(out));
endmodule
不知道问什么 ’timescale，‘include，’idefine，这些命令在modelsim中不能用总是显示错误？

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