library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock_10Hz is
port(reset:in std_logic;
clk_in:in std_logic;
clk_out: out std_logic_vector(21 downto 0));
end clock_10Hz ; architecture behavioral of clock_10Hz is
signal clk_cnt:std_logic_vector( 21 downto 0);
signal clk_bit: std_logic; begin
gen_clock:process(clk_in ,reset)is
begin if(reset='0') then
clk_cnt <="0000000000000000000000";
clk_bit <= '0'; elsif rising_edge(clk_in)then
if(clk_cnt=1199999)then
clk_cnt <="0000000000000000000000";
clk_bit<=not clk_bit; else
clk_cnt<=clk_cnt+1; end if; end if; end process; clk_out<=clk_cnt; end behavioral; 此帖出自小平头技术问答