编了一个顶层的模块 将M0、M1、M2、M3、组合起来但是M2的输出端口write，和M1的Dout端口不见了请大神帮忙！   module mpeg_2ts(TS_OUT,TS_IN,CLK,SYNC,RESET,DIN,CLK_W,EN);
   
    parameter data_width = 8;
 
 output [data_width - 1 : 0] TS_OUT;
 input [data_width - 1 : 0] TS_IN;
 input [data_width - 1 : 0] DIN;
 input CLK,SYNC,RESET,CLK_W,EN;
      wire stack_7_full,write_to_stack,write,read,read_from_stack;
      wire[7:0] control_data_out,control_data_in,Dout;
 control M0(.ts_out(TS_OUT),
            .read(read_from_stack),
            .ts_in(TS_IN),
            .sync(SYNC),
            .clk(CLK),
            .rst(RESET),
            .control_data_out(control_data_out),
               .stack_7_full(stack_7_full));
                     
 data M1(.Dout(control_data_in),
         .Din(DIN),
         .En(EN),
         .clk_w(CLK_W),
         .rst(RESET));  syn_write M2(.clk_300KHz(CLK_W),
              .clk_10MHz(CLK),
              .write(write_to_stack),
              .rst(RESET));
  
   
    fifo M3(.control_data_out(control_data_out),                
         .stack_7_full(stack_7_full),
         .write_to_stack(write),
         .read_from_stack(read),
         .control_data_in(Dout),
         .clk(CLK),
         .rst(RESET)); endmodule 此帖出自小平头技术问答