各位好!
我有一个xilinx ML506的板子,下了个简单的组合逻辑电路测试 结果OK。
然后下个时序逻辑就出错了。。。
我的代码如下:
module LED( c, my_clk
);
input my_clk;
output reg c;
wire clk;
initial begin
c = 1;
end
always @(posedge clk) begin
c <= ~c;
end
div_clk uut (
.my_clk(my_clk),
.clk(clk)
);
endmodule
module div_clk(my_clk, clk
);
input my_clk;
output reg clk;
reg [15:0] counter;
initial begin
counter = 0;
end
always @(posedge my_clk) begin
if (counter == 10000) begin
counter <= 0;
clk <= ~clk;
end
else begin
clk <= clk;
counter <= counter + 1;
end
end
endmodule
约束文件如下:
#" PlanAhead Generated physical constraints "
NET "c" LOC = H18
#"Created by Constraints Editor (xc5vsx50t-ff1136-1) - 2011/04/01"
NET "my_clk" TNM_NET = my_clk
TIMESPEC TS_my_clk = PERIOD "my_clk" 1 ms HIGH 50% INPUT_JITTER 10 us
#"Created by Constraints Editor (xc5vsx50t-ff1136-1) - 2011/04/02"
OFFSET = OUT 50 ns AFTER "my_clk"
结果是:c信号对应管脚的灯一直亮着!当我把counter设为500 时,灯则是闪一下就灭了!
求教了 ! thx
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