module state(rst,clk,bale,iow,la,ld,dout,ad);
input rst;
input clk;
input bale;
input iow;
input[3:0] la;
input[7:0] ld;
output[7:0] dout;
output[7:0] ad;
reg[7:0] dout;
reg[7:0] ad;
parameter st0=4'b0001,st1=4'b0010,st2=4'b0100,st3=4'b1000;
reg[3:0] current_st,next_st;
always @(posedge clk or negedge rst)
begin
if(!rst)
current_st<=st0;
else
current_st<=next_st;
end
always @(current_st or bale or iow)
begin
case (current_st)
st0:
begin
if(bale)
next_st=st1;
else
next_st=st0;
end
st1:
begin
if(!iow)
next_st=st2;
else
next_st=st0;
end
st2:
begin
next_st=st3;
end
st3:
begin
next_st=st0;
end
default:
begin
next_st=st0;
end
endcase
end
always @(current_st or la or ld)
begin
case (current_st)
st0:begin
dout<=0;
ad<=0;
end
st1:begin
dout<=0;
ad<=0;
end
st2:begin
case (la)
4'b000:
begin
dout<=ld;
end
4'b001:
begin
ad<=ld;
end
default:begin
dout<=ld;
end
endcase
end
st3:begin
dout<=dout;
ad<=ad;
end
endcase
end
endmodule
在quartus中编译出现这样的警告:
Warning (10240):
Verilog HDL Always Construct warning at state.v(61): inferring latch(es) for variable "dout", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at state.v(61): inferring latch(es) for variable "ad", which holds its previous value in one or more paths through the always construct
Warning: Latch ad[0]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal la[1]
Warning: Latch ad[1]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal la[1]
Warning: Latch ad[2]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal la[1]
Warning: Latch ad[3]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal la[1]
Warning: Latch ad[4]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal la[1]
Warning: Latch ad[5]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal la[1]
Warning: Latch ad[6]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal la[1]
Warning: Latch ad[7]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal la[1]
怎么解决啊?
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