写了一个顶层文件，如下
entity top is
    Port ( CLK : in  STD_LOGIC;
           RX : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           GPIO : inout  STD_LOGIC_VECTOR (0 downto 0);
           TX : out  STD_LOGIC;
     INT : out STD_LOGIC_VECTOR (0 downto 0));
end top;
architecture Behavioral of top is
signal S_gpio :std_logic_vector(0 downto 0);
COMPONENT system
PORT(
fpga_0_RS232_RX_pin : IN std_logic;
fpga_0_clk_1_sys_clk_pin : IN std_logic;
fpga_0_rst_1_sys_rst_pin : IN std_logic;   
fpga_0_Generic_GPIO_GPIO_IO_pin : INOUT std_logic_vector(0 to 0);      
fpga_0_RS232_TX_pin : OUT std_logic
);
END COMPONENT;
COMPONENT test21
PORT(
clk : IN std_logic;         
INT1 : OUT std_logic_vector(0 to 0);
INT2 : OUT std_logic_vector(0 to 0)
);
END COMPONENT;


begin
Inst_system: system PORT MAP(
  fpga_0_RS232_RX_pin => RX,
  fpga_0_RS232_TX_pin => TX,
  fpga_0_Generic_GPIO_GPIO_IO_pin => S_gpio,
  fpga_0_clk_1_sys_clk_pin => clk,
  fpga_0_rst_1_sys_rst_pin => rst
);
Inst_test21: test21 PORT MAP(
  clk => clk,
  INT1 => INT,
  INT2 => S_gpio
);
end Behavioral;


综合时发现错误
ERROR:Xst:528 - Multi-source in Unit <top> on signal <S_gpio>; this signal is connected to multiple drivers 此帖出自小平头技术问答