本帖最后由 fu4730 于 2019-8-21 16:21 编辑

arm初始化程序如下：
static void MX_FMC_Init(void)
{

  /* USER CODE BEGIN FMC_Init 0 */

  /* USER CODE END FMC_Init 0 */

  FMC_NORSRAM_TimingTypeDef Timing = {0};
  FMC_SDRAM_TimingTypeDef SdramTiming = {0};

  /* USER CODE BEGIN FMC_Init 1 */

  /* USER CODE END FMC_Init 1 */

  /** Perform the SRAM1 memory initialization sequence
  */
  hsram1.Instance = FMC_NORSRAM_DEVICE;
  hsram1.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
  /* hsram1.Init */
  hsram1.Init.NSBank = FMC_NORSRAM_BANK1;
  hsram1.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
  hsram1.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
  hsram1.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;
  hsram1.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
  hsram1.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
  hsram1.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
  hsram1.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
  hsram1.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
  hsram1.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
  hsram1.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
  hsram1.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
  hsram1.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
  hsram1.Init.WriteFifo = FMC_WRITE_FIFO_DISABLE;
  hsram1.Init.PageSize = FMC_PAGE_SIZE_NONE;
  /* Timing */
  Timing.AddressSetupTime = 15;
  Timing.AddressHoldTime = 15;
  Timing.DataSetupTime = 30;
  Timing.BusTurnAroundDuration = 0;
  Timing.CLKDivision = 0;
  Timing.DataLatency = 0;
  Timing.AccessMode = FMC_ACCESS_MODE_A;
  /* ExtTiming */

  if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)
  {
    Error_Handler( );
  }


arm主程序中向fpga写数据程序如下：
*(SRAM_BANK1_BASE_ADDRESS + 0x0002) = 0xff00;
fpga 程序如下：
pll_100M        pll_100M_inst (
        .inclk0 ( clk ),
        .c0 ( clk_100M )
        );
        
assign FMC_Data = ((flag)?FMC_Data_out:16'bz);

always@(posedge clk_100M)begin
   DO_EN <= 0;
   if((ne1 == 0)&&(nwe == 1)&&(noe == 0))//&&(nwait == 1'b0))
           flag <= 1;
        else if((ne1 == 0)&&(nwe == 0)&&(noe == 1))//&&(nwait == 1'b0))
           flag <= 0;
end

always@(posedge clk_100M)begin
if((flag == 0)&&(Addr == 8'h2))begin  //&&(DO_EN == 1'b0)
           //if(delay_1clk == 1)begin
                  // delay_1clk <= 0;
              DO[15:0] <= FMC_Data;
                end
          // else
                  // delay_1clk <= delay_1clk + 1;
end

endmodule

keil5中memory观察到的数据如下：
fpga signaltap ii观察到的数据如下：
问题：为什么signaltap ii观察到的数据是arm向fpga写了四个地址，实际上arm只写了一个地址