姹傚姪锛歷ivado涓嬬敤ILA璋冭瘯PL绔€昏緫闂

2020-01-27 13:50发布

鍚勪綅澶т緺锛氭渶杩戞垜鍦╲ivado涓嬭窇xilinx瀹樻柟娴嬭瘯DDR鐨別xample锛孌DR鏄寕鍦≒L绔殑锛?鐢熸垚bit鏂囦欢涓嬭浇鍒版澘瀛愪笅锛屾€绘槸鏃犳硶鎵惧埌hw_ila锛屽苟涓旀彁绀簑arning锛?br /> WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
INFO: [Labtools 27-1434] Device xc7z030 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7z030_1 and the probes file E:/pl_ddr3/pl_ddr3/pl_ddr3.runs/impl_1/debug_nets.ltx.
The device design has 0 ILA core(s) and 0 VIO core(s). The probes file has 4 ILA core(s) and 0 VIO core(s).
Resolution:
1. Reprogram device with the correct programming file and associated probes file OR
2. Goto device properties and associate the correct probes file with the programming file already programmed in the device.
鎴戣瘯杩囬噸鏂扮敓鎴愶紝浣跨敤set up debug绛夌瓑閮藉嚭涓嶆潵锛屾湁鐩稿悓缁忓巻鐨勫厔寮熸寚鐐逛笅闂鍑哄湪鍝噷锛屼竾鍒嗘劅璋紒
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9条回答
tmkdfan
2020-01-28 05:39
swi2008 鍙戣〃浜?2016-11-11 14:11
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