FPGA

DDR MAP pack 1107

2020-02-02 10:28发布

站内问答 / FPGA
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Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOBM component because the site type selected is not compatible.

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOBM was chosen because the IO contains symbols and/or properties consistent
   with differential master usage. Please double check that the types of logic
   elements and all of their relevant properties and configuration options are
   compatible with the physical site type of the constraint.

   Summary:
   Symbols involved:
           PAD symbol "cntr0_ddr_ck" (Pad Signal = cntr0_ddr_ck)
           BUFINV symbol
   "XLXI_5/top_00/iobs_00/infrastructure_iobs_00/gen_clk[0].obufds_clk/OBUFDS"
   (Output Signal = cntr0_ddr_ck)
   Component type involved: IOBM
   Site Location involved: A10
   Site Type involved: LOWCAPIOB

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOBS component because the site type selected is not compatible.

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOBS was chosen because the IO contains symbols and/or properties consistent
   with differential slave usage. Please double check that the types of logic
   elements and all of their relevant properties and configuration options are
   compatible with the physical site type of the constraint.

   Summary:
   Symbols involved:
           PAD symbol "cntr0_ddr_ck_n" (Pad Signal = cntr0_ddr_ck_n)
           SlaveBuffer symbol
   "XLXI_5/top_00/iobs_00/infrastructure_iobs_00/gen_clk[0].obufds_clk/SLAVEBUF.
   DIFFOUT" (Output Signal = cntr0_ddr_ck_n)
   Component type involved: IOBS
   Site Location involved: B10
   Site Type involved: LOWCAPIOB


Mapping completed.
See MAP report file "top_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors   :   2
Number of warnings :   1
希望大佬们可以解释一下如何改正，最近在学ddr的过程中遇到的，多谢
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4条回答
aaaaaaddaw
2020-02-02 15:59
`timescale 1ns / 1ps
`include "../rtl/ddr_parameters_0.v"

module ddr_infrastructure_iobs_0
  (
   input      clk,
   output  [`CLK_WIDTH-1:0]   ddr_ck,
   output  [`CLK_WIDTH-1:0]   ddr_ck_n
   );

   wire [`CLK_WIDTH-1:0]      ddr_ck_q;
   wire                       vcc;
   wire                       gnd;

   assign vcc         = 1'b1;
   assign gnd         = 1'b0;

   //***************************************************************************
   // Memory clock generation
   //***************************************************************************
   
   genvar clk_i;
   generate
   for (clk_i = 0; clk_i < `CLK_WIDTH; clk_i = clk_i+1) begin : gen_clk

       ODDR #
         (
          .SRTYPE       ("SYNC"),
          .DDR_CLK_EDGE ("OPPOSITE_EDGE")
          )
      oddr_clk
       (
         .Q(ddr_ck_q[clk_i]),
         .C(clk),
         .CE(vcc),
         .D1(gnd),
         .D2(vcc),
         .R(gnd),
         .S(gnd)
       );

     OBUFDS obufds_clk
       (
         .I(ddr_ck_q[clk_i]),
         .O(ddr_ck[clk_i]),
         .OB(ddr_ck_n[clk_i])
       );
   end
   endgenerate

endmodule

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