刚刚学verilog,我输入好程序，编译时，总是显示建立的项目名字没有定义这个错误是怎么回事，试了几个程序都是这样的状况
Error (12007): Top-level design entity "banjiaqi" is undefined
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
        Error: Peak virtual memory: 451 megabytes
        Error: Processing ended: Sat Aug 08 22:31:38 2015
        Error: Elapsed time: 00:00:05
        Error: Total CPU time (on all processors): 00:00:02