本人初学Xilinx，写了一个简单的小程序，配置引脚时出现以下warning
WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
   that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
   IOB component <clk> is placed at site <P78>. The corresponding BUFG component
   <clk_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y3>. There is only a select set
   of IOBs that can use the fast path to the Clocker buffer, and they are not
   being used. You may want to analyze why this problem exists and correct it.
   This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was
   applied on COMP.PIN <clk.PAD> allowing your design to continue. This
   constraint disables all clock placer rules related to the specified COMP.PIN.
   The use of this override is highly discouraged as it may lead to very poor
   timing results. It is recommended that this error condition be corrected in
   the design.