仿真后就一直是这个界面
二分频器的源程序
module divider_frequency(clk_in,rst,clk_out);
input clk_in,rst;
output clk_out;
wire clk_out;
reg clk_temp;
always@(posedge clk_in or negedge rst)
begin
  if(!rst)clk_temp=0;
  else
    clk_temp=~clk_temp;
end
assign clk_out=clk_temp;
endmodule
二分频器的测试程序
`timescale 1ns/1ns
module divider_frequency_tb();
reg clk_in;
reg rst;
wire clk_out;
divider_frequency u0(
  .clk_in(clk_in),
  .rst(rst),
  .clk_out(clk_out)
  );
initial
begin
  clk_in=0;
  rst=0;
  #100 rst=1;
end
always#1000 clk_in=~clk_in;
endmodule