bzy812 发表于 2014-3-24 11:05
vhdl

给你个例子 看看吧。
entity example2 is
port (in1, in2 : in bit;
         clk : in bit;
        out1, out2 : out bit );
end example2;
architecture rt1 of example2 is
      attribute syn_keep : boolean;
      signal and_out, keep1, keep2: bit;
      attribute syn_keep of keep1, keep2 : signal is true;
begin
       and_out <= in1 and in2;
       keep1 <= and_out;
       keep2 <= and_out;
process(clk)
begin
if (clk'event and clk = '1') then
   out1 <= keep1;
   out2 <= keep2;
end if;
end process;
end rt1;