代码贴上，没测试，不保证能用，能理解就理解，不教会，不解释
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-- Company:
-- Engineer:
--
-- Create Date:    13:24:23 09/09/2016
-- Design Name:
-- Module Name:    WideCntr - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity WideCntr is
generic(A_SIZE:integer:=5); -- VEC=A_SIZE*2**A_SIZE,3=>24,4=>64,5=>160,6=>384
port(
        clk        :        in std_logic;
        rst        :        in std_logic;
        p                :        in std_logic;
        addr        :        in std_logic_vector(0 to A_SIZE-1);
        cntr        :  out std_logic_vector(0 to A_SIZE-1)
);
end WideCntr;

architecture Behavioral of WideCntr is
        type RAM_TYPE is array(0 to 2**A_SIZE-1) of std_logic_vector(0 to A_SIZE-1);
        signal ram:RAM_TYPE:=(others=>(others=>'0'));
       
        signal p_cntr:std_logic_vector(0 to A_SIZE);
        signal p_c_clr:std_logic;
        signal cy:std_logic;       
        signal ram_addr:std_logic_vector(0 to A_SIZE-1);
        signal ram_data:std_logic_vector(0 to A_SIZE);
       
begin

process(clk)
begin
if clk'event and clk='1' then
if rst='1' then
        p_cntr<=(others=>'0');
else
        if p='1' then
                if p_c_clr='1' then
                        p_cntr(0)<='0';
                        p_cntr(1 to A_SIZE)<=p_cntr(1 to A_SIZE)+1;
                else
                        p_cntr<=p_cntr +1;
                end if;
        end if;
end if;
end if;
end process;

process(clk)
begin
if clk'event and clk='1' then
        ram(conv_integer(ram_addr)) <=ram_data(1 to A_SIZE);
end if;
end process;

        ram_data<=(others=>'0') when rst='1' else ('0'&ram(conv_integer(ram_addr)))+cy;
       
process(clk)
begin
if clk'event and clk='1' then
if rst='1' then
        ram_addr<=ram_addr+1;
        p_c_clr<='0';
        cy<='0';
else
        p_c_clr<='0';
        cy<='0';
        ram_addr<=conv_std_logic_vector(1,A_SIZE);
        if p_cntr(0)='1' then
                cy<='1';
                p_c_clr<='1';
        elsif ram_data(0)='1' then
                cy<='1';
                ram_addr<=ram_addr+1;
        end if;
end if;
end if;
end process;


        cntr<=p_cntr(1 to A_SIZE) when addr=0 else ram(conv_integer(addr));

end Behavioral;