cnb12345 发表于 2016-7-15 14:55
看不到图

把图上了，帮忙看看代码行不

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--实体
entity da1_test is
    port (
          clk:in STD_LOGIC  ;  --系统主时钟
          da1_clk:out std_logic;  --给DA的时钟
          da1_d:out std_logic_vector(13 downto 0)  --给DA的数据
                        );
end da1_test;
------------------------------------------------
architecture topdesign_arch of da1_test is
------------------------------------------------
signal count_clk:std_logic_vector(13 downto 0);
------------------------------------------------

begin
-------------------------------------------------
da1_clk <=clk;  --给DA的时钟
--da_clk <=not count_clk(0);  --给DA的时钟
-------------------------------------------------

process(clk)
begin
        if clk'event and clk='1' then
-------------------------------------------------
           count_clk<=count_clk+1;
           da1_d<=count_clk(13 downto 0);
-------------------------------------------------
        end if ;
-------------------------------------------------
end process;
-------------------------------------------------
end topdesign_arch;