使用quartus进行modelsim仿真时,出现了一些问题。打开RTL仿真后,modelsim导入后报错。
# -- Compiling module altera_pll
# ** Error: d:/quartus/quartus/eda/sim_lib/altera_lnsim.sv(237): (vlog-60) SystemVerilog packages are not currently supported.
# ** Error: d:/quartus/quartus/eda/sim_lib/altera_lnsim.sv(238): near "localparam": syntax error
# ** Error: d:/quartus/quartus/eda/sim_lib/altera_lnsim.sv(588): near "integer": expecting: IDENT THIS
# ** Error: d:/quartus/quartus/eda/sim_lib/altera_lnsim.sv(707): near "altera_lnsim_functio": expecting: STRING
# ** Error: d:/quartus/quartus/eda/sim_lib/altera_lnsim.sv(814): near "altera_lnsim_functio": expecting: STRING
# ** Error: d:/quartus/quartus/eda/sim_lib/altera_lnsim.sv(1189): near "altera_lnsim_functio": expecting: STRING
# ** Error: d:/quartus/quartus/eda/sim_lib/altera_lnsim.sv(3019): near "altera_lnsim_functio": expecting: STRING
# ** Error: d:/quartus/quartus/eda/sim_lib/altera_lnsim.sv(3434): near "altera_lnsim_functio": expecting: STRING
# ** Error: D:/modelsim/win32/vlog failed.
# Error in macro ./top_run_msim_rtl_verilog.do line 24
# D:/modelsim/win32/vlog failed.
# while executing
# "vlog -sv -work altera_lnsim_ver {d:/quartus/quartus/eda/sim_lib/altera_lnsim.sv}"
请大神帮我
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请问是我的工程代码有错,还是测试文件有错
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