always@(negedge clk_100ms , negedge rest)
begin
        if(EN==0)       
                LED<=LED+1;
        if(rest==0)
                LED<=0;
end

我的EN又不是敏感信号怎么还会有这样的错误？

Error (10200): Verilog HDL Conditional Statement error at couter.v(27): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct