ERROR:NgdBuild:770 - IBUFG
   'ddr3_inter_inst/u200_iodelay_ctrl/se_clk_ref.u_ibufg_clk_ref' and BUFG
   'clk_gen_inst/clkout1_buf' on net 'clk200_ref' are lined up in series.
   Buffers of the same direction cannot be placed in series.
ERROR:NgdBuild:924 - input pad net 'clk200_ref' is driving non-buffer
   primitives:
我用clock wizard，输入时钟125，出来200M时钟和400M时钟，给DDR3 mig使用，MAP时遇到这么一个问题，不知道怎么解决，望高手解答。